Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Chih-Chiang Wang

Tze-Liang Lee

Chien-Hao Chen

Li-Ting Wang

Chun-Feng Nieh

Li-Ping Huang

Hsun Chang

Shih-Chang Chen

Kuo-Hua Pan

Yi-Ming Sheu

Hsien-Chin Lin

Keh-Chiang Ku

Jyh-Haur Wang

Carlos Hernando Diaz

Ying-Shiou Lin

Keh-Chiang Kuo

An electric package device is provided, including a first chip and a second chip. The first chip includes a first conductive pad. The second chip includes a second conductive pad. The second conductive pad couples to the first conductive pad through a connection wire. In some embodiments, the first chip includes a first signal control circuit that receives, in response to a selection signal, one of multiple input signals as a first signal, filters the first signal, and outputs the filtered first signal, as a second signal, from the first conductive pad to the second conductive pad.

Electronic package device and method of operating the same

A digital-to-analog converter and a digital-to-analog conversion method thereof are provided. The digital-to-analog conversion method includes: converting a digital data signal into an analog data signal in a first cycle according to a clock signal, resetting the analog data signal in a second cycle according to the clock signal and a reset signal corresponding to a first reset level, and compensating for a voltage level of the reset analog data signal in the second cycle according to a second reset level, so that the voltage level of the reset analog data signal is the second reset level. The second reset level is higher or lower than the first reset level.

Digital-to-analog converter and digital-to-analog conversion method thereof

A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Sigma-delta analog-to-digital converter capable of reducing idle tones while alternately conducting signal conversion and comparator offset calibration

A device and a method for digital to analog conversion are provided. The device contains a signal generation circuit and a conversion circuit. The signal generation circuit generates two reset signals which are a first reset signal and a second reset signal. The two reset signals are mutually inverted digital signals and contain the same number of bits. The conversion circuit converts a digital data signal into an analog data signal when a first clock signal is at a first level, and generates the analog data signal at two reset levels respectively according to the two reset signals when the first clock signal is at a second level.

Device and method for digital to analog conversion

An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

Semiconductor device including an arrangement for suppressing short channel effects

A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

Method of enhancing dopant activation without suffering additional dopant diffusion

A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

Semiconductor device having ultra-shallow and highly activated source/drain extensions

A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Growing community of inventors

Hsinchu, Taiwan

Chih-Chiang Wang