Sony Corporation

Sony Electronics Inc

Chih-Chiang Tseng

Hsin-Ley Suzanne Chen

Patrick Chuang

Mu-Hsiang Huang

Jae-Hyeong Kim

Robert Haig

Kookhwan Kwon

A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.

Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus

An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1&#xd7; mode) and high-speed rate (2&#xd7; mode) to a device under test. In 1&#xd7; mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2&#xd7; mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.

Test semiconductor device in full frequency with half frequency tester

A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed together to form the dual operation decoding signal. The memory device receives a read address and a write address consecutively in one cycle to generate the dual operation decoding signal. A single operation, such as a read only operation or a write only operation, can be performed as well as the dual operation of performing the read operation and the write operation in the same cycle.

Performing read and write operations in the same cycle for an SRAM device

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Fremont, CA, United States of America

Chih-Chiang Tseng