Mstar Semiconductor, Inc.

Chih Chiang Hsu

Jian-Kao Chen

Yu-Ming Lin

A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.

Display timing control circuit with adjustable clock divisor and method thereof

A backlight control circuit and method thereof are provided to control the backlight of a backlight module so as to enhance the dynamic contrast ratio and save power. The backlight control circuit includes an average luminance detection circuit, a luminance distribution detection unit, a pulse width control circuit and a pulse width modulator. The average luminance detection circuit detects the average luminance of a frame which includes a plurality of pixels; the luminance distribution detection unit detects the pixel luminance distribution of the frame; the pulse width control circuit generates a pulse width control signal according to the average luminance and the pixel luminance distribution of the frame; and the pulse width modulator generates a pulse width modulation (PWM) signal according to the pulse width control signal, so as to control the backlight of the backlight module.

Backlight control circuit and method thereof

A decoding method and apparatus capable of automatically adjusting a sampling period is provided. The decoding apparatus decodes a serial code including at least one header pulse and a plurality of data pulses. The decoding apparatus includes a detecting unit for detecting the header pulse to generate an initialization signal, a determining unit for determining a sampling period according to the initialization signal and a pulse width of one of the data pulses, and a decoding unit for decoding the data pulses according to the sampling period.

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Hsinchu Hsien, Taiwan

Chih Chiang Hsu