Fih (hong Kong) Limited

Taiwan Semiconductor Manufacturing Comp. Ltd.

Shenzhen Futaihong Precision Industry Co., Ltd.

Sutech Trading Limited

Acemach Co., Ltd.

Silverstone Technology Co., Ltd.

Industrial Technology Research Institute

Shenzhen China Star Optoelectronics Technology Co., Ltd.

Wistron Neweb Corporation

Aten International Co., Ltd.

Can Do Gmbh

Chih-Chiang Chang

Zheng Shi

Mu-Wen Yang

Yung-Chow Peng

Tao Su

Chung-Chieh Yang

Chung-Peng Hsieh

Chung-Ting Lu

Zhi-Yun Shen

Wen-Shen Chou

Zhi Bin Li

Ming-Hua Yu

Kun-Mu Li

Su-Jen Sung

Chia-Ho Chen

Wen-Ze Liu

Nai Chen Cheng

Shang-Chih Hsieh

Chia-Chan Chen

Qing-Meng Li

Yao-Hao Chang

Hsueh-Chang Sung

Li-Li Su

Chin-Hua Wen

Yung-Shun Chen

Yang-Yang Cui

Chia-Wei Hu

Yee-Chia Yeo

Chii-Horng Li

Chien-Hung Zordius Chen

Chien-I Kuo

Hsin-Hung Chen

Yu-Tao Yang

Chang-Yu Wu

Yung-Hsu Chuang

Che-Yu Lin

Wen-Chu Hsiao

Tai-Yi Chen

Wei-Chih Hsieh

Bindu Madhavi Kasina

Brady Yang

Si-Quan Chen

Xiang-Guo Zhao

Ya-Min Ren

Yang-Yu Li

Chun-Lan Hsiao

Yang Chung-Chieh

Jing-Cheng Lin

Wei-Yang Lee

Chien-Hung Chen

Ta-Pen Guo

Yu Zhang

Chia-Pin Lin

Yen-Ting Chen

Osamu Takahashi

Chien-Chang Su

Yueh-Chuan Lee

Mu-Jen Huang

Chih-Hao Chen

Mao-Hsuan Chou

Shui-Jin Dong

Kewei Zuo

Tsung-Hsi Yang

Chien Rhone Wang

Ming-Zhang Kuo

Chih-Wei Lai

Cho-Yi Lin

Chiung-Ting Ou

Zhi-Qiang Xiao

Chu-Fu Chen

Jen-Hang Yang

Xiao-Liang Wei

Min-Tar Liu

Yung-Chang Yen

Chung-Chi Wen

Han-Chang Lin

Hong-Wei Zhang

Pao-Chun Lin

Ding-Yuan Wang

Wei-Siang Yang

Chen-Chao Chang

Hai-Shen Feng

Sang Hoo Dong

Bang-Ting Yan

Chien-wei Lee

Kuan-Ying Lin

Teng-Yin Cheng

Cha-Yu Chang

Ji-Chern Lin

Ting-Yi Huang

Tzu-Yi Chuang

Syuan-You Liao

Pan-Pan Wang

Guo-Guang Ren

Yan-Ting Lin

Chih Teng Hsu

Ping-Hsiang Huang

Ling-Sheng Yang

Hsin-hung Chen

A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing a portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing a semiconductor layer in the recess, and forming a first dielectric layer interposing the semiconductor layer and the dummy gate structure. The semiconductor layer covers at least a portion of the first dielectric layer. The method also includes modifying a shape of the semiconductor layer to expose the portion of the first dielectric layer, depositing a second dielectric layer covering the semiconductor layer and the portion of the first dielectric layer, and replacing the dummy gate structure with a metal gate structure.

Epitaxial features in semiconductor devices and manufacturing method of the same

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

Photosensing pixel including self-aligned light shielding layer

Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.

Optical sensing device having inclined reflective surface

A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.

Delay-locked loop circuit and method

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Source/drain formation with reduced selective loss defects

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Circuitry and method for reducing environmental noise

A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Nanosheet semiconductor device and method for manufacturing the same

The present disclosure relates to an integrated circuit. The integrated circuit includes a conductive interconnect disposed on a dielectric over a substrate. An interfacial layer is arranged along an upper surface of the conductive interconnect. A liner is arranged along a lower surface of the conductive interconnect. The liner and the interfacial layer surround the conductive interconnect. A middle layer is located over the interfacial layer and has a bottommost surface over the dielectric. A bottommost surface of the interfacial layer and the bottommost surface of the middle layer are both above a top of the conductive interconnect.

Electro-migration barrier for interconnect

A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

Digitally controlled delay line circuit and method

A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Semiconductor devices including decoupling capacitors and methods of manufacturing thereof

A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

On-chip oscilloscope

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Automatic generation of sub-cells for an analog integrated circuit

An image control device and an image control method are provided. The image control device includes a control command output port, an image input port, a processor and an image output unit. The control command output port transmits a scene switching command to an image source device; the image input port receives an image stream from the image source device; the processor is coupled to the image input port and the control command output port to retrieve a first image and a second image from the image stream, wherein the second image corresponds to the scene switching command; the image output unit is coupled to the processor and outputs the first image and the second image, wherein the first image is displayed in a first display area and the second image is displayed in a second display area.

Device and method for image control

Growing community of inventors

Taipei Hsien, Taiwan

Chih-Chiang Chang