Taiwan Semiconductor Manufacturing Comp. Ltd.

Trend Micro Inc.

National Chung Shan Institute of Science and Technology

Aimtron Technology Corp.

Advanced Analog Technology, Inc.

Chih-Chia Chen

Hung-Chih Lin

Mill-Jer Wang

Hao Chen

Ching-Nen Peng

Chao-Yang Yeh

Meng-lin Chung

Chin-Chou Liu

Mark Shane Peng

Sa-Lly Liu

Ze-Ming Wu

Kuan-Yu Lin

Yung-Chih Chen

Sheng-Chi Hsieh

Shr-an Su

Chao-Yu Chen

Peng-Shih Pu

Cheng-Hsin Hsu

Chang-Lun Lee

Bei-Huw Shen

Li-Fu Ding

Wen-Yen Hsieh

Chien-Chuan Chung

Chin-Lung Chiang

A method for preparing a wear-resistant hybrid, includes (A) providing nano-silica with hydroxyl groups on its surface to react with an isocyanate-based silane to form silica with silyl groups; (B) subjecting the silica with silyl groups to a hydrolytic condensation reaction by using a sol-gel technology to form highly bifurcated Si-HB nanoparticles with hydroxyl groups; (C) providing a diisocyanate to react with a polyol to form a urethane pre-polymer; and (D) subjecting the Si-HB nanoparticles with hydroxyl groups to an addition reaction with the urethane pre-polymer and with a chain-extending reagent to form a hybrid of Si-polyurethane (PU/Si-HB), whereby a wear-resistant hybrid of Si-polyurethane is prepared.

Method for preparing wear-resistant-hybrid

Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.

Bandgap reference apparatus and methods

Unwanted web contents are detected in an endpoint computer. The endpoint computer receives a web page from a website. The reputation of the website is determined and the web page is scanned for malicious codes to protect the endpoint computer from web threats. To further protect the endpoint computer from web threats including mutating unwanted web contents, page structure traits of the web page are generated and compared to page structure traits of other web pages detected to contain unwanted web contents.

Methods and systems for detecting unwanted web contents

A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.

3D IC testing apparatus

A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

Switched capacitor comparator circuit

A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.

A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

Tool and method for modeling interposer RC couplings

A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.

Reduced swing signal

Detection for pharming attacks and specifically for changes in name-to-IP resolutions on a computer system using rules is described. The DNS settings and the Hosts file on a computer system are monitored and their modification information is saved as a part of the historical data over time. When an IP address is determined for a host name, various rules are applied to the IP address in connection with the saved historical data, such that each rule produces a score based on various criteria. Different rules may have different weights assigned to their scores. The scores of all the rules are summed up to produce a final score. If the final score is above a predefined value, then there is a suspicious change in the IP address, and an alert is sent. Otherwise, the host name and the IP address are saved as a part of the historical data.

System for detecting change of name-to-IP resolution

An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.

Reducing the switching noise on substrate with high grounding resistance

A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage.

Voltage level shifter with voltage boost mechanism

A first to an n-th current sources supply a first to an n-th charging currents, respectively. A sequence control circuit allows an x-th charging current of the first to the n-th charging currents to charge a capacitor for generating an x-th soft-start signal. The variable x is an integer and satisfies an inequality of n&#x2267;x&#x2267;1. Before a y-th charging current is allowed to charge the capacitor for generating a y-th soft-start signal, the sequence control circuit stops charging the capacitor by the x-th charging current and discharges the capacitor toward a ground potential. The variable y is an integer different from the variable x and satisfies an inequality of n&#x2267;y&#x2267;1.

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Taipei, Taiwan

Chih-Chia Chen