Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih Chi Hsiao

Yung-Chow Peng

Wei-Ting Lin

Chien-Wen Chen

Mu-Jen Huang

Tsung-Hsin Yu

Kuo-Ji Chen

Jui-Feng Kuan

Wen-Ju Preet Yang

Wei-Yi Hu

Yu-Ren Chen

Jian-Yi Li

Jill Liu

A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Semiconductor device design method, system and computer program product

A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.

In-phase grouping for voltage-dependent design rule

In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

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Hsinchu, Taiwan

Chih Chi Hsiao