Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

National Taiwan University

Chih-Cheng Lu

Syun-Ming Jang Jang

Chu-Yun Fu

Hsin Chia Chen

Fang-Shi Jordan Lai

Chin-Hao Chang

Yung-Fu Lin

Cheng Yen Weng

Hsu-Feng Hsueh

Manoj M Mhala

Cheng-Da Huang

Weng Chang

Chuan-Ping Hou

Ching-Ray Chang

Jen-Hwa Hsu

Wen Yao Chang

Syun-Ming Jeng

Chang Wen

Jang Syun Ming

Jen-Tzong Jeng

Stacey Fu

Bor-Lin Lai

Van-Su Luong

A single bridge magnetic field sensor includes a fluxguide mounted to a surface of a substrate. A bridge unit includes first, second, third, and fourth magnetoresistive elements mounted around the fluxguide and mounted on the surface of the substrate. A switching circuit is electrically connected to two voltage inputs, two grounding terminals, two voltage output terminals, and the four magnetoresistive elements. The switching circuit can proceed with circuit switching according to a magnetic field in each axis direction to be measured, thereby changing electrical connection between the voltage inputs, the grounding terminals, the voltage output terminals, and the four magnetoresistive elements. A measuring unit is electrically connected to the two voltage output terminals and the four magnetoresistive elements. The magnetoresistances of the four magnetoresistive elements measured by the measuring unit and output voltages of the voltage output terminals can be used to obtain a magnetic field measurement result.

Single bridge magnetic field sensor

The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

Apparatus and method for measuring degradation of CMOS VLSI elements

A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.

Pipeline analog-to-digital converter

A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor, a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.

Nonvolatile analog memory

A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.

A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

Method of achieving improved STI gap fill with reduced stress

A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF, SiFor NFand SiFto remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

Shallow trench isolation method for reducing oxide thickness variations at different pattern densities

A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed 'L' shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Test region layout for shallow trench isolation

A method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer including providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing the carbon doped oxide layer according to an oxidizing treatment to convert at oxidize at least a portion of the carbon doped oxide layer to produce silicon oxide; and, wet etching the silicon oxide to substantially remove the silicon oxide.

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Taipei, Taiwan

Chih-Cheng Lu