Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Industrial Technology Research Institute

Gemtek Technology Co., Ltd.

Institute for Information Industry

Mxtran Inc.

California Institute of Technology

Asustek Computer Inc.

Pegatron Corporation

Chih-Cheng Lin

Hsin-Chang Lee

Chia-Jen Chen

Yun-Yue Lin

Anthony Yen

Ta-Cheng Lien

Ping-Hsun Lin

Jeng-Horng Chen

Chin-Hsiang Lin

Pei-Cheng Hsu

Chyi-Ming Leu

Jian-Ru Lin

Ziwei Fang

Huang-Lin Chao

I-Ming Chang

Shih-Chieh Chen

Amo Chen

Chung-Shi Liu

Chung-Liang Cheng

Yao-Ching Ku

Wei-Jen Lo

Chun-I Wu

Hsueh-Wen Tsau

Shih-Cheng Wang

Yen-Cheng Ho

Chi-Fu Tseng

Chen-Kuo Chiang

Hsuan-Chen Chen

Chin-Sheng Lin

Cheng-Chia Kuo

Mark Chien

Wei-Shiuan Chen

Chia-Shiung Tsai

Chi-Ming Yang

Shinn-Sheng Yu

Chih-Tsung Shih

Ping-Yin Liu

Chih-Chiang Tu

Chun-Lang Chen

Chyi Shyuan Chern

Wei-Ming You

Tsiao-Chen Wu

Jong-Yuh Chang

Che-Wei Chang

Kai-Yin Liu

Chue San Yoo

Bang-Chein Ho

Chien-Sheng Chen

Rui Wang

Nai-Chang Yeh

Hui-Min Huang

Chi-Ying Wu

Hsueh-Yi Liao

Yu-Ju Kuo

Chi-Chao Hsu

Jeng-Shin Ma

Yung-Pin Liu

Hao-Ting Li

Amö Chen

Dah-Chung Oweyang

Hsueh-Liang Hung

Chen-Hsuan Lu

Yun-yue Lin

A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.

Photomask including fiducial mark and method of making a photomask

A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.

Photomask and method of fabricating a photomask

The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.

Pellicle assembly and method for advanced lithography

A method of making a semiconductor device includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern.

Photomask including fiducial mark and method of making a semiconductor device using the photomask

A method of forming graphene on a flexible substrate includes providing a polymer substrate including a metal structure and providing a carbon source and a carrier gas. The method also includes subjecting the polymer substrate to a plasma enhanced chemical vapor deposition (PECVD) process and growing a graphene layer on the copper structure.

Methods and devices for graphene formation on flexible substrates by plasma-enhanced chemical vapor deposition

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

Semiconductor device structure

A method of making a semiconductor device includes forming at least one fiducial mark on a photomask outside of a pattern region of the photomask, and the at least one fiducial mark includes identifying information for the photomask. The method includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern. The method includes transferring the pattern from the photomask to a wafer.

Photomask including fiducial mark and method of making semiconductor device using the photomask

A classification model building apparatus and a classification model building method thereof are provided. The classification model building apparatus introduces a clustering algorithm to assist in training a deep learning model for classification and takes a sum of a clustering loss function, a center concentration loss function and a classification loss function multiplied by different weights, respectively, as a total loss function for training the deep learning model. Based on the total loss function, the classification model building apparatus adjusts parameters of the deep learning model through a backpropagation algorithm to build a classification model.

Classification model building apparatus and classification model building method thereof

A motion recognition apparatus extracts a plurality of first motion feature vectors within a period of time, and extracts a plurality of second motion feature vectors within another period of time closely next to the period of time. The apparatus calculates and sequences the distances between each of the plurality of first motion feature vectors and the plurality of cluster centroids to generate a corresponding first cluster centroid sequence respectively, and calculates and sequences the distances between each of the plurality of second motion feature vectors and the plurality of cluster centroids to generate a corresponding second cluster centroid sequence respectively. The apparatus recognizes a first segment motion, a second segment motion, and a whole motion based on the number of appearances of the cluster centroid in the first cluster centroid sequences, the second cluster centroid sequences and both of them respectively.

Motion recognition apparatus and method

The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.

A power switch comprises a SPDT switch having a common side and a switch side; a first isolation switch electrically connected at the common side of the SPDT switch and a second isolation switch electrically connected at the switch side of the SPDT switch; a microprocessor for detecting a current direction and controlling the conduction state of one of the first isolation switch and the second isolation switch in response to the detected current direction; and a power converter converting AC power to DC power for powering the first isolation switch, the second isolation switch and the microprocessor.

Power switch and control method thereof

A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

Lithography mask with both transmission-type and reflective-type overlay marks and method of fabricating the same

A photomask includes a pattern region and a plurality of defects in the pattern region. The photomask further includes a first fiducial mark outside of the pattern region, wherein the first fiducial mark includes identifying information for the photomask, the first fiducial mark has a first size and a first shape. The photomask further includes a second fiducial mark outside of the pattern region. The second fiducial mark has a second size different from the first size, or a second shape different from the first shape.

Photomask including fiducial mark, method of patterning the photomask and method of making semiconductor device using the photomask

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Semiconductor device structure and method for forming the same

Growing community of inventors

Kaohsiung, Taiwan

Chih-Cheng Lin