Tsinghua University

Pixart Imaging Incorporated

Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Applied Research Laboratories

Egis Technology Inc.

Chih-Cheng Hsieh

Chien-Chang Huang

Ching-Wei Chen

Shang-Fu Yeh

Min-Yang Chiu

Tzu-Hsiang Hsu

Meng-Fan Chang

Chun-Kai Liu

Hann-Huei Tsai

Chien-Wen Chen

Chin-Fong Chiu

Kea-Tiong Tang

Kuo-Wei Cheng

Ka-Yi Yeh

Syuan-Hao Sie

Yen-Kai Chen

You-Shin Chen

Chiao-Jen Cheng

Wen-Hsu Chang

A method is provided to operate an image sensor, including the following steps: comparing a first threshold with multiple first frame-difference signals to generate a first region of interest (ROI) address, wherein each of multiple first frame-difference signals is generated by a corresponding pixel, in multiple pixels, operating during a first time frame and a second time frame, wherein multiple pixels are arranged in multiple columns and multiple rows; identifying edge columns and edge rows in the first ROI address; adjusting, according to the edge columns and the edge rows, the first ROI address to generate a second ROI address; and outputting a ROI image according to the second ROI address and multiple second frame-difference signals generated by multiple pixels operating during the second time frame and a third time frame after the second time frame.

Image sensor and method of operating the same

An image sensor chip and a sensing method thereof are disclosed. The image sensor chip includes pixel units. Each pixel unit includes a reset switch, a sampling switch, a light sensing element, a capacitor, and an output circuit. The sampling switch is coupled between the reset switch and the light sensing element. The capacitor is coupled between the sampling switch and the output circuit. The output circuit outputs difference information corresponding to a difference between a plurality of sensing results of the light sensing element in different frame periods to a corresponding readout line. The sampling switch has an ON-time length during an exposure period and an OFF-time length during a readout and clean-up period. A ratio of the ON-time length to the OFF-time length is related to a ratio of a capacitance of the light sensing element to a capacitance of the capacitor.

Image sensor chip and sensing method thereof

An image sensor integrated with a convolutional neural network computation circuit is provided. The image sensor includes: a pixel array including pixels divided into pixel groups, wherein each pixel converts a light signal into a PWM signal; a convolution computation circuit controlling a turn-on time of a corresponding weighted current according to the first PWM signal of each pixel, and accumulating the weighted currents into an integrated current; a comparison circuit converting the integrated current into a second PWM signal and comparing it with that of an adjacent pixel group to output a larger one; and a classification circuit quantizing the second PWM signal to a quantization value according to a weight of a node in a fully-connected layer corresponding to each pixel group, accumulating the quantization values of all pixel groups into a feature value, and comparing the feature value with a feature threshold to obtain a classification result.

Image sensor integrated with convolutional neural network computation circuit

An image sensor chip and a sensing method thereof are provided. The image sensor chip includes a pixel array. The pixel array includes a plurality of pixel units, and each of the pixel units includes a light sensing circuit, a reset switch and an output circuit. The reset switch is coupled to a first terminal of the light sensing circuit. The reset switch resets the light sensing circuit during reset period. The output circuit is coupled to the first terminal of the light sensing circuit. The output circuit of the pixel unit outputs difference information corresponding to the difference between the first sensing result of the light sensing circuit in a first frame period and the second sensing result of the light sensing circuit in a second frame period after the first frame period to a corresponding one of a plurality of readout lines of the pixel array.

A method for integrating a processing-in-sensor unit and an in-memory computing includes the following steps. A providing step is performed to transmit the first command signal and the initial data to the in-memory computing unit. A converting step is performed to drive the first command signal and the initial data to convert to a second command signal and a plurality of input data through a synchronizing module. A fetching step is performed to drive a frame difference module to receive the input data to fetch a plurality of difference data. A slicing step is performed to drive a bit-slicing module to receive the difference data and slice each of the difference data into a plurality of bit slices. A controlling step is performed to encode the difference address into a control signal, and the in-memory computing unit accesses each of the bit slices according to the control signal.

Method and system for integrating processing-in-sensor unit and in-memory computing unit

A processing device for position sensing includes a plurality of light sensors, a signal processing unit, a current mirror unit and a transforming unit. The light sensors are spaced apart from each other and sense a light field to generate a plurality of position sensing current signals. The signal processing unit receives the position sensing current signals and provides a load isolation, so as to generate a first current signal and a second current signal. The second current signal is transmitted to a node. The first and second current signals respectively correspond to a first group and a second group of light sensors. The current mirror unit mirrors the first current signal to a third current signal. The third current is transmitted to the node. The transforming unit transforms a differential current signal formed by the second and third current signals on the node to a voltage signal.

Processing device for position sensing comprising a transforming differential current signal to a voltage signal performance

The present invention is related to an optical recognition system and a method thereof, and more particularly to an optical recognition system and a method that adopts a single-slope analog-to-digital converter to proceed a single-slope analog-to-digital conversion in order to have an image with a wide dynamic range.

Optical recognition system and method thereof

A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.

Pixel array module with self-test function and method thereof

The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.

Circuit sharing time delay integrator

A pinned photodiode sensor with gate-controlled SCR switch includes a pinned photodiode and a gate-controlled SCR switch. The SCR switch includes a P-type substrate, an N&#x2212; doped region, and an N+ doped region formed on the substrate; a P+ doped region formed on the N&#x2212; doped region; an oxide layer formed on the P substrate, the N&#x2212; doped region, the N+ doped region, and the P+ doped region; and a gate formed above the P substrate and the N&#x2212; doped region. The gate includes a P+ doped region and an N+ doped region. During an exposure procedure, a depletion region will not reach the interface between the oxide layer and the substrate, thereby preventing dark current leakage.

Pinned photodiode sensor with gate-controlled silicon-controlled rectifier transfer switch and method of formation

A CMOS image sensor includes a semiconductor substrate; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region and a surface pinning diffusion region overlying the charge-accumulating diffusion region; a transfer transistor, wherein the transfer transistor has a transfer gate comprising a protruding first gate segment with a first gate dimension and a second gate segment with a second gate dimension that is smaller than the first gate dimension. A first overlapping portion between the protruding first gate segment and the charge-accumulating diffusion region is greater than a second overlapping portion between the second gate segment and the charge-accumulating diffusion region.

CMOS image sensor

This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.

Method for fabricating CMOS image sensor

A method of forming a solid-state image sensor is provided. The method includes the steps of forming a plurality of photosensor elements on a substrate; forming a plurality of color filters on the plurality of photosensors; forming a light blocking member between adjacent color filters; and forming a plurality of microlenses on the plurality of color filters. Each photosensor with each corresponding color filter and microlens is used for receiving an incident light of specific spectrum.

Solid-state image sensor for improving sensing quality and manufacturing method thereof

A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.

Growing community of inventors

Hsinchu, Taiwan

Chih-Cheng Hsieh