Micron Technology Incorporated

Micro Technology, Inc.

Chih-Chen Cho

Zhongze Wang

Todd R Abbott

Er-Xuan Ping

Jigish D Trivedi

Charles H Dennison

Richard H Lane

Gurtej S Sandhu

Sanh D Tang

Shubneesh Batra

Howard Kirsch

Mike P Violette

Robert James Burke

Xianfeng Zhou

Anuradha Iyengar

Eugene R Gifford

John D Trivedi

Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

Multiple-depth STI trenches in integrated circuit fabrication

A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Applying epitaxial silicon in disposable spacer flow

A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.

Cross diffusion barrier layer in polysilicon

Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

Methods for making semiconductor structures having high-speed areas and high-density areas

A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

Method of forming a field effect transistor with halo implant regions

A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

FET having epitaxial silicon growth

Method of forming a field effect transistor

A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited within an etched via and is contacted with the conductive plug.

Backend metallization method and device obtained therefrom

Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

Integrated transistor circuitry

According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

Suppression of cross diffusion and gate depletion

A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.

Growing community of inventors

Boise, ID, United States of America

Chih-Chen Cho