Texas Instruments Corporation

Other

Chih-Chen Cho

Bruce E Gnade

Douglas M Smith

Howard R Beratan

Robert H Havemann

Walter Marvin Duncan

Ming J Hwang

Scott Robert Summerfelt

Jeffrey A McKee

Hung-Yu Liu

Jiong-Ping Lu

Jules D Levine

William R McKee

Shin-Puu Jeng

Kyung-Ho Park

Isamu Asano

Howard L Tigelaar

Richard A Stoltz

Wei-Yung Hsu

Robert M Wallace

Tae S Kim

Robert Yung-Hsi Tsu

William C Ackerman

Alan C Seabaugh

Dirk N Anderson

Yasushiro Nishioka

John Mark Anthony

Shou-Kong Fan

Yoshimitsu Tamura

Wiley P Kirk

Jin Changming

Gregory C Johnston

Tsen H Lin

Joe X Zhou

An integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Integrated circuit and method

A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning ( ) the silicon substrate. A passivation layer is formed ( ), which may comprise arsenic, germanium, or CaF , among others. The lattice matched layer is then grown ( ) on the passivation layer.

method of forming lattice matched layer over a surface of a silicon substrate

A chemical mechanical polishing machine with ultrasonic vibration is disclosed. The chemical mechanical polishing machine (,) includes a movable abrasive surface (,). A wafer holder (,) holds a wafer (,) in contact with the abrasive surface (,), and a vibration generator (,) vibrates the wafer (,) during polishing. The ultrasonic vibration agitates the slurry and provides an additional degree of motion between the wafer and the abrasive surface, thereby increasing the speed and uniformity of the polishing.

Chemical mechanical polishing machine with ultrasonic vibration and method

An optical coating for an uncooled focal plane array detector where the optical coating comprises a porous film. The porous film preferably comprises a xerogel.

High MTF optical coating for hybrid UFPA's

A method for protecting metal (,) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (,), smile oxidation, and sidewall (,) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (,) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.

Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing

Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (,) over an oxidizable section (,) of the semiconductor device. The protective cover (,) is operable to at least inhibit oxidation of the oxidizable section (,). While the oxidizable section (,) is covered, an oxide structure (,) is formed. The oxide structure (,) is operable to at least ameliorate etch damage to the semiconductor device.

Post-etch treatment of a semiconductor device

A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.

Method for a semiconductor device having reduced contact resistance and leakage

This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The method may comprise providing a substrate comprising a microelectronic circuit and a porous silica layer, the porous silica layer having an average pore diameter between 2 and 80 nm; and heating the substrate to one or more temperatures between 100 and 490 degrees C. in a substantially halogen-free atmosphere, whereby one or more dielectric properties of the porous dielectric are improved. In some embodiments, the atmosphere comprises a phenyl-containing atmosphere, such as hexaphenyldisilazane. In some embodiments, the method further comprises cooling the substrate and exposing the substrate to a substantially halogen-free atmosphere comprising either a phenyl-containing compound, such as hexaphenyldisilazane; or a methyl-containing compound, such as hexamethyldisilazane. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Porous dielectric material with improved pore surface properties for

A TiN.sub.x layer is formed by disposing a substrate (18) in a chamber (12). A first reactant gas (40) comprising Ti, a second reactant gas (42) and a third reactant gas (44) comprising N are introduced into the chamber (12). By controlling the ratio of the first, second and third reactant gasses (40, 42, 44), TiN.sub.x is deposited onto a surface (28) of the substrate (18), where x is between zero and one.

Method of forming an electrical contact in a substrate

A contact and method of forming a contact. A layer of titanium (112) is deposited. Then, a RTP anneal is performed to react the titanium layer (112) with underlying silicon (112) to form a silicide layer (114). After the RTP anneal, a layer of tungsten-nitride (116) is deposited as a barrier layer. The metal interconnect layer (118) is then formed over the tungsten-nitride layer (116).

Tungsten-nitride for contact barrier application

This is a device and method of forming such, wherein the device has an amorphous 'TEFLON' (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.

Method of forming a low-k layer in an Integrated circuit

A thermal detector having an optical coating comprising a porous film 64. The porous film preferably comprises a xerogel or aerogel and is greater than 80% porous. An optional optical impedance matching layer 66 may be deposited over the porous film 64. Advantages include decreased thickness of the thermal sensor, improved acuity of the image produced by the system, lower manufacturing temperatures, and the ability to use electrodes that are opaque to infrared energy.

Low mass optical coating for thin film detectors

In order to provide a thermally stable diffusion barrier for a contact, a layer of titanium is formed on the patterned substrate. A layer of tungsten nitride is formed on the titanium layer. After an annealing step, an interfacial layer and a layer of titanium nitride are formed between the substrate and a tungsten layer. These layers provide a diffusion barrier which is more thermally stable than a titanium nitride layer applied directly on the substrate and permits the formation of a contact structures that can withstand subsequent high temperature steps.

Method for fabricating thermally stable contacts with a diffusion

Method of forming a low-K layer in an integrated circuit

This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Growing community of inventors

Richardson, TX, United States of America

Chih-Chen Cho