Intel Corporation

Netlist, Inc.

Chih-Cheh Chen

Michael T Klinglesmith

David M Lee

Malay Trivedi

Sin Sim Tan

Mohan Nair

Scott H Milton

Suresh S Chittor

Tina C Zhong

Itay Franko

Russell J Wunderlich

Jeekyoung Park

Jonathan Nick Spitz

Peter J Elardo

John Zulauf

Jerry Alston

Patrick Lee

Amit Kumar Srivastava

Janusz Jurski

David N Lombard

James Mitchell

Piotr Michael Kwidzinski

Jordan A Horwich

Christopher Van Beek

Chris Van Beek

Jordan Horwich

A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

Computer memory expansion device and method of operation

Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

External resource discovery and coordination in a data center

An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

Dynamic lane access switching between PCIe root spaces

Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Method to coordinate system boot and reset flows and improve reliability, availability and serviceability (RAS) among multiple chipsets

Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.

Multicast support on a switch for PCIe endpoint devices

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

Coherent variable length reads from system memory

Coherent variable length reads which implicates multiple cache lines by

Growing community of inventors

Portland, OR, United States of America

Chih-Cheh Chen