International Business Machines Corporation

Globalfoundries Inc.

Industrial Technology Research Institute

Infineon Technologies Ag

Adeia Semiconductor Bonding Technologies Inc.

National Applied Research Laboratories

United Microelectronics Corp.

Elpis Technologies Inc.

Other

Novatek Microelectronics Corp.

Globalfoundries U.S. 2 LLC

Internatoinal Business Machines Corporation

Chih-Chao Yang

Lawrence Alfred Clevenger

Daniel C Edelstein

Baozhen Li

Shom Ponoth

David V Horak

Oscar Van Der Straten

Koichi Motoyama

Keith Kwong Hon Wong

Timothy Joseph Dalton

Charles W Koburger, Iii

Michael Rizzolo

Juntao Li

Conal Eugene Murray

Ashim Dutta

Alexander Reznicek

Junli Wang

Theodorus E Standaert

Praneet Adusumilli

Chanro Park

Carl John Radens

Louis L Hsu

Takeshi Nogami

Terry Allen Spooner

Haining S Yang

Kangguo Cheng

Hsueh-Chung Chen

Benjamin David Briggs

Ruilong Xie

Jack Allan Mandelman

William R Tonti

Hong He

Louis Lu-Chen Hsu

Griselda Bonilla

Marc Adam Bergendahl

Takashi Ando

Yun-Yu Wang

Steven J Holmes

Ping-Chuan Wang

Hosadurga K Shobha

Thomas M Shaw

Yunpeng Yin

Andrew Herbert Simon

Rajiv V Joshi

Kirk David Peterson

Su Chen Fan

Nicholas Anthony Lanzillo

Ronald G Filippi

Xiao Hu Liu

Bruce Bennett Doris

Soon-Cheon Seo

Yann Mignot

Son Van Nguyen

Ekmini Anuja De Silva

Hayden C Cranford, Jr

Elbert Emin Huang

Brent A Anderson

Mukta G Farooq

Christopher J Penny

Stephen McConnell Gates

Matthew Earl Colburn

Wai-Kin Li

Donald Francis Canaperi

Oleg Gluschenkov

Christian Lavoie

John Edward Sheets, Ii

Timothy Dooling Sullivan

Qinghuang Lin

Jon Michael Slaughter

Thomas W Dyer

John Kenneth DeBrosse

Ali Khakifirooz

Veeraraghavan S Basker

Clement Hsingjen Wann

Sivananda K Kanakasabapathy

Alfred Grill

Xiuyu Cai

Injo Ok

Kisik Choi

Chi-Chun Liu

Satyanarayana Venkata Nitta

Vamsi Krishna Paruchuri

Stephen Mark Rossnagel

Kafai Lai

Choonghyun Lee

Chen Zhang

Yun Yu Wang

Vijay Narayanan

Hemanth Jagannathan

Julien Frougier

Balasubramanian Pranatharthiharan

Sampath Purushothaman

Fee Li Lie

Sanjay C Mehta

Chih-Chien Liu

Roy Rongqing Yu

Seyoung Kim

Robert C Wong

Hans-Joachim Barth

William Paul Hovis

A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

Local interconnects having different material compositions

A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Backside power rail with tight space

An MRAM device is provided. The MRAM device includes a first dielectric cap layer formed on an underlying layer, a second dielectric cap layer formed on the first dielectric cap layer, the first dielectric cap layer including a lower-κ material than that of the second dielectric cap layer. The MRAM device also includes a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer, an MRAM stack formed on the BEC, and wherein the second dielectric cap layer surrounds an upper portion of the BEC.

Layered bottom electrode dielectric for embedded MRAM

A method to form a semiconductor structure for a magnetoresistive random-access memory (MRAM) device where the material for the top electrode and the bottom electrode is deposited in a single process. The method includes conformally depositing an electrode material over a magnetic tunnel junction (MTJ) pillar, under the MTJ pillar, around a spacer encapsulating and extending above the MTJ pillar. The method includes recessing the electrode material to form a thinner portion of the electrode material over the MTJ pillar. The thinner portion of the electrode material forms a thinner portion of the electrode material over the MTJ pillar that is a top electrode. The portion of the electrode material under the MTJ pillar forms a bottom electrode that is thicker than the top electrode.

Magnetoresistive random-access memory with top and bottom electrodes deposited in unison

A semiconductor device and formation thereof. The semiconductor device includes a memory device located on top of a first bottom interconnect, wherein the first bottom interconnect is embedded in a first dielectric layer. The semiconductor device further includes a second bottom interconnect embedded in the first dielectric layer, wherein the second bottom interconnect is adjacent to the first bottom interconnect. A top surface of the second bottom interconnect is recessed relative to a top surface of the first bottom interconnect.

Recessed local interconnect semiconductor memory device

A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Locally widened profile for nanoscale wiring structure

A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

Air gap in beol interconnect

A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

Double patterning with selectively deposited spacer

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a bottom electrode layer surrounded by a bottom dielectric layer; forming an etch-stop layer on top of the bottom electrode layer and the bottom dielectric layer; creating an opening in the etch-stop layer to expose a top surface of the bottom electrode layer; forming a first ferromagnetic layer on top of the bottom electrode layer and the etch-stop layer, with a portion of the first ferromagnetic layer filling the opening in the etch-stop layer; forming a tunnel barrier layer and a second ferromagnetic layer on top of the first ferromagnetic layer; patterning the second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. A structure formed thereby is also provided.

MRAM structure with a T-shaped ferromagnetic layer

Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Back-end-of-line thin film resistor

An MRAM device is provided. The MRAM device includes a semiconductor device comprising a bottom contact electrode (BEC), and an MRAM stack formed on the BEC. A width of an upper portion of the BEC is less than a width of the MRAM stack.

MRAM bottom electrode contact with taper profile

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

MRAM device with octagon profile

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Magneto-resistive random access memory with hemispherical top electrode

Growing community of inventors

Glenmont, NY, United States of America

Chih-Chao Yang