International Business Machines Corporation

Globalfoundries Inc.

Industrial Technology Research Institute

Infineon Technologies Ag

Adeia Semiconductor Bonding Technologies Inc.

National Applied Research Laboratories

United Microelectronics Corp.

Elpis Technologies Inc.

Other

Novatek Microelectronics Corp.

Globalfoundries U.S. 2 LLC

Internatoinal Business Machines Corporation

Chih-Chao Yang

Lawrence Alfred Clevenger

Daniel C Edelstein

Baozhen Li

Shom Ponoth

David V Horak

Oscar Van Der Straten

Keith Kwong Hon Wong

Koichi Motoyama

Timothy Joseph Dalton

Charles W Koburger, Iii

Michael Rizzolo

Juntao Li

Conal Eugene Murray

Alexander Reznicek

Junli Wang

Praneet Adusumilli

Ashim Dutta

Theodorus E Standaert

Chanro Park

Carl John Radens

Louis L Hsu

Takeshi Nogami

Terry Allen Spooner

Haining S Yang

Kangguo Cheng

Hsueh-Chung Chen

Benjamin David Briggs

Jack Allan Mandelman

William R Tonti

Hong He

Ruilong Xie

Louis Lu-Chen Hsu

Griselda Bonilla

Marc Adam Bergendahl

Takashi Ando

Yun-Yu Wang

Steven J Holmes

Ping-Chuan Wang

Hosadurga K Shobha

Thomas M Shaw

Yunpeng Yin

Andrew Herbert Simon

Rajiv V Joshi

Kirk David Peterson

Su Chen Fan

Ronald G Filippi

Xiao Hu Liu

Bruce Bennett Doris

Soon-Cheon Seo

Yann Mignot

Nicholas Anthony Lanzillo

Hayden C Cranford, Jr

Ekmini Anuja De Silva

Son Van Nguyen

Elbert Emin Huang

Brent A Anderson

Mukta G Farooq

Christopher J Penny

Stephen McConnell Gates

Matthew Earl Colburn

Wai-Kin Li

Donald Francis Canaperi

Oleg Gluschenkov

Christian Lavoie

John Edward Sheets, Ii

Timothy Dooling Sullivan

Qinghuang Lin

Thomas W Dyer

John Kenneth DeBrosse

Ali Khakifirooz

Veeraraghavan S Basker

Clement Hsingjen Wann

Sivananda K Kanakasabapathy

Alfred Grill

Xiuyu Cai

Injo Ok

Chi-Chun Liu

Kisik Choi

Satyanarayana Venkata Nitta

Vamsi Krishna Paruchuri

Stephen Mark Rossnagel

Kafai Lai

Choonghyun Lee

Chen Zhang

Yun Yu Wang

Vijay Narayanan

Hemanth Jagannathan

Balasubramanian Pranatharthiharan

Julien Frougier

Sampath Purushothaman

Fee Li Lie

Sanjay C Mehta

Jon Michael Slaughter

Chih-Chien Liu

Roy Rongqing Yu

Seyoung Kim

Robert C Wong

Hans-Joachim Barth

William Paul Hovis

Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Back-end-of-line thin film resistor

An MRAM device is provided. The MRAM device includes a semiconductor device comprising a bottom contact electrode (BEC), and an MRAM stack formed on the BEC. A width of an upper portion of the BEC is less than a width of the MRAM stack.

MRAM bottom electrode contact with taper profile

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

MRAM device with octagon profile

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Magneto-resistive random access memory with hemispherical top electrode

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

Damascene MRAM device

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Fabrication of embedded memory devices utilizing a self assembled monolayer

A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Metal-insulator-metal capacitor structure with enlarged capacitor area

An MRAM device is provided. The MRAM device includes a first electrode, an MRAM stack formed on the first electrode, a hardmask structure formed on the MRAM stack, and a second electrode formed on the hardmask structure. A width of an upper portion of the hardmask structure is less than a width of the MRAM stack.

Conical magnetic random access memory pillar structures

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a magnetic tunnel junction (MTJ) stack; forming a first dielectric layer to a level above a tunnel barrier layer of the MTJ stack, the first dielectric layer partially covering the MTJ stack with a top surface of the MTJ stack being exposed; depositing an etch-stop layer covering the top surface of the MTJ stack and a top surface of the first dielectric layer; depositing a second dielectric layer covering the etch-stop layer; forming an opening in the second dielectric layer; removing a portion of the etch-stop layer above the top surface of the MTJ stack; and forming a top contact by depositing a conductive material in the opening. An MRAM structure formed thereby is also provided.

MRAM device structure

A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.

Advanced metal interconnect

Growing community of inventors

Glenmont, NY, United States of America

Chih-Chao Yang