Macronix International Co., Ltd.

Accton Technology Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Accion Technology Corporation

Chih-Chang Hsieh

Hang-Ting Lue

Kuo-Pin Chang

Teng-Hao Yeh

Chih-Ping Chen

Hsu-Shui Liu

Chih-Wei Hu

Tzu-Hsuan Hsu

Hsiang-Pang Li

Yung-Chun Li

Yu-Ming Chang

Chih-Kuo Chang

Yung-Kai Lin

Ti-Wen Chen

Wei-Ting Hsiao

Kai Lo

Chun-Hsiung Hung

Shih-Hung Chen

Yen-Hao Shih

Shuo-Nan Hung

Tei-Wei Kuo

I-Ru Liu

Yuan-Hao Chang

Ming-Chang Kuo

Yi-Hsuan Hsiao

Yi-Chang Chen

Hung-Sheng Chang

Ti Wen Chen

Chang-Cheng Liu

Chung-Chieh Hsu

Shih-Lin Huang

Hang Ting Lue

Yang-Te Fu

Shih-Fu Huang

Chen-Jun Wu

Yung Chun Li

Yungchun Li

Chian-Kun Chan

Chung-chieh Hsu

Chian-kun Chan

Chun-Teng Hsu

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

Memory device for computing in-memory

A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

Memory device and compensation method of data retention thereof

A memory device and a data approximation search method thereof are proposed. The memory device includes a plurality of selection switch pairs, a plurality of memory cell string pairs, a sense amplifier, and a page buffer. The selection switch pairs receive multiple search data pairs, respectively. The memory cell string pairs are respectively coupled to a global bit line through the selection switch pairs. Each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. The sense amplifier obtains multiple search results according to the current on the global bit line and at least one reference currents respectively corresponding to at least one similarity. The page buffer records the search results and generates similarity information by accumulating the search results.

Memory device and data approximation search method thereof

A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

Ternary content addressable memory

A wireless access point device includes a main frame, an antenna module, a signal transceiving element, an unlocking assembly and a fastener. The main frame includes a casing and a first connection portion formed with a fastening recess, connected to the casing and communicates with the internal space. The signal transceiving element is located in the casing. The antenna module includes a waveguide and a second connection portion disposed on one end of the waveguide. The second connection portion is detachably connected to the first connection portion to couple to the signal transceiving element. The unlocking assembly is movably located in the fastening recess. The fastener includes a buckle, and an elastic member that is connected to the second connection portion and the buckle. The antenna module is fixed on the main frame when the buckle is inserted into the fastening recess.

Wireless access point device

A wireless access point device includes a main frame, a transmission assembly, an antenna module and a fixing assembly. The main frame includes a casing and a first connection portion connected to the casing. The transmission assembly is disposed in an internal space of the casing and provided with a signal transceiving element. The antenna module includes a waveguide, a second connection portion and a positioning recess. The second connection portion is disposed on the waveguide and detachably connected to the first connection portion to be coupled to the signal transceiving element. The positioning recess is formed on the second connection portion. The fixing assembly is movably disposed on the first connection portion. The antenna module is thereby fixed on the casing, when the second connection portion and the first connection portion are fixed through the fixing assembly removably inserting into the positioning recess.

A waterproof assembly includes a casing, a gasket, and a cap. The casing has an opening. The gasket includes a main body and a protruding portion. The main body has a first circular raised structure configured to abut against an inner surface of the casing. The protruding portion is connected to the main body and is configured to at least partially protrude out of the casing through the opening. The cap is configured to abut against a side of the main body away from the opening. The cap has a through hole configured to be aligned with the protruding portion. The casing further has a plurality of fixing members configured to abut against a side of the cap away from the gasket.

Waterproof assembly

A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C() and C(), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S, an intermediate program stage S, and a final program stage Sto memory cells in the first and second stacks. In a programming order the final program stage Sis applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage Shas already been applied to the memory cells in any neighboring levels (levels i+1 and i&#x2212;1). The intermediate program stage Sis applied only to memory cells for which the preliminary program stage Shas already been applied to the cells in any neighboring levels (levels i+1 and i&#x2212;1).

3D memory with staged-level multibit programming

An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.

Semiconductor apparatus with transportable edge ring for substrate transport

The present invention discloses an antenna apparatus. The antenna apparatus includes a first antenna array and a second antenna array. The first antenna array includes multiple first radiating elements for transmitting radio signals of a first frequency. The second antenna array includes multiple second radiating elements for transmitting radio signals of a second frequency, wherein the first and second radiating elements are arranged in a staggered manner; wherein each of the first radiating elements is disposed between two of the second radiating elements; and wherein each of the second radiating elements is disposed between two of the first radiating elements.

Antenna apparatus and the MIMO communication device using the same

A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.

Programming multibit memory cells

This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage.

Electronic device, non-volatile memorty device, and programming method

A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

Memory device and associated erase method

A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level.

Memory array and operating method of same

Growing community of inventors

Hsinchu, Taiwan

Chih-Chang Hsieh