Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Tokyo Electron Limited

Chiew Wah Yap

Yelehanka Ramachandramurthy Pradeep

Mei Sheng Zhou

Yung Fu Chong

Pradeep Yelehanka

Eng Hua Lim

Dong Kyun Sohn

Sung Mun Jung

Zheng Zou

Yun Ling Tan

Kazuki Narishige

Liang Li

Jie Yu

Seiichi Watanabe

Sripad Sheshagiri Nagarad

Xiaoyu Chen

Kenji Komatsu

Hwa Weng Koh

Takehito Watanabe

Koji Kawamura

Louis Lim

Xue Chun Dai

Bin Zhao

Nguyen Lac

Wee Teck Tan

Minghui Fan

Nitin Kamat

Hao Nong

Xinhe Jerry Lim

Jianfeng Xu

Manni Lal

Yi Hao Ng

Zhenkang Max Liang

Ting Huo

Yujun Nicholas Loo

Chai Jin Chua

Li Jin

Dali Liu

A substrate processing method performed in a chamber of a substrate processing apparatus is provided. The chamber includes a substrate support, an upper electrode, and a gas supply port. The substrate processing method includes (a) providing the substrate on the substrate support; (b) supplying a first processing gas into the chamber; (c) continuously supplying an RF signal into the chamber while continuously supplying a negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber; and (d) supplying a pulsed RF signal while continuously supplying the negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber. The process further includes repeating alternately repeating the steps (c) and (d), and a time for performing the step (c) once is 30 second or shorter.

Substrate processing method and substrate processing apparatus

Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures

An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.

Integrated circuit system including nitride layer technology

Method of forming almost L-shaped spacer for improved ILD gap fill

A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer. There is then etched selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated with the encapsulating layer. Finally, there is then stripped, while employing a second etch method which employs a second etchant, from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer the encapsulating layer. The method may be employed for stripping from a gate electrode within a field effect transistor (FET) a patterned dielectric cap layer formed upon the gate electrode while not etching a gate dielectric layer upon Which is formed the gate electrode within the field effect transistor (FET).

Selective etch method for selectively etching a multi-layer stack layer

A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

Method for forming an L-shaped spacer with a disposable organic top coating

Growing community of inventors

Singapore, Singapore

Chiew Wah Yap