Silterra Malaysia Sdn. Bhd.

Chartered Semiconductor Manufacturing Ltd (Corporation)

Chiew Sin Ping

Hitomi Watanabe

Naoto Inoue

Min Paek

Sang Yeon Kim

Inki Kim

Wan Gie Lee

Choong Shiau Chien

Zadig Lam

Yung-Tao Lin

Charlie Tay

Ch'ng Toh Ghee

Ramakrishnan Rajagopal

Chang Gi Lee

Chwa Siow Lee

A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.

Semiconductor device with dual gate oxides

A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.

Shallow trench isolation

A new method of forming non-volatile memory cells with an improved bottom silicon dioxide layer of the O&mdash;N&mdash;O has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is grown overlying the semiconductor substrate. A polysilicon layer is deposited overlying the tunneling dielectric layer. Nitrogen is implanted into the polysilicon layer to form a nitridized surface region. The polysilicon layer and the tunneling dielectric layer are then patterned to form floating gates. A bottom silicon dioxide layer is grown overlying the floating gates by thermal oxidation of the polysilicon layer. The nitridized surface region reduces the rate of thermal oxidation and creates a smooth surface. A silicon nitride layer is deposited overlying the bottom silicon dioxide layer. A top silicon dioxide layer is formed overlying the silicon nitride layer to complete the O&mdash;N&mdash;O stack. A conductive layer, that may comprise polysilicon, is deposited overlying the top silicon dioxide layer. The conductive layer, the top silicon dioxide layer, the silicon nitride layer, and the bottom silicon dioxide layer are patterned to form control gates and to complete the non-volatile memory cells.

Method to form non-volatile memory cells

Growing community of inventors

Kuala Lumpur, Malaysia

Chiew Sin Ping