International Business Machines Corporation

Infineon Technologies Ag

Other

Chienfan Yu

Wesley Charles Natzle

David M Dobuzinsky

Leping Li

Clifford Owen Morgan, Iii

Cong Wei

James Albert Gilhooly

Richard L Kleinhenz

Hongwen Yan

Shwu-Jen Jeng

Qingyun Yang

Len Yuan Tsou

Jeffrey J Brown

David V Horak

Richard Stephan Wise

Lee Chen

Johnathan E Faltermeier

David Edward Kotecki

Joyce C Liu

Sadanand Vinayak Deshpande

Hung Y Ng

Jin J Wu

Michael Maldei

Ying Di Zhang

Herbert Lei Ho

Babar Ali Khan

Gary Bela Bronner

Byeong Yeol Kim

Rama Divakaruni

Larry Alan Nesbit

Maheswaran Surendra

Michael D Armacost

Naim Moumen

Robert B Laibowitz

Colin J Brodsky

Rajesh Rengarajan

Erick G Walton

Jeremy K Stephens

Rebecca D Mih

Munir D Naeem

Dan Mihai Mocuta

Scott W Crowder

Peter Richard Duncombe

John W Golz

David C Ahlgren

John Chester Malinowski

Larry Clevenger

Teresa Jacqueline Wu

James Patrick Norum

William M Chu

Munir-ud-Din Naeem

Prakash Chimanlal Dev

George A Kaplita

Paul Wensley

Thomas Rupp

John Preston Benedict

Delores A Bennett

Derek Chen

Frederick William Buehrer

Senthil K Srinivasan

Anne C Friedman

Garrett W Oakley

Babar A Kanh

James C Brighten

Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. Control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.

High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

Reduced cap layer erosion for borderless contacts

A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

Vapor phase etch trim structure with top etch blocking layer

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH F or CH F , the carbon source is preferably one of CO or CO, and the oxidant is preferably O . The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.

Selective nitride: oxide anisotropic etch process

A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.

Wet etch reduction of gate widths

A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si&mdash;C-containing film or combinations thereof.

Method to controllably form notched polysilicon gate structures

A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Dual layer hard mask for eDRAM gate etch process

A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Dual mask process for semiconductor devices

Detection of the endpoint for removal of a target film overlying a stopping film by removing the target film with a process that selectively generates a chemical reaction product (for example, ammonia when polishing a wafer with a nitride film in a slurry containing KOH) with either the target or stopping film, and monitoring the level of chemical reaction product as the target film is removed. The reaction product is extracted as a gas from the slurry and monitored using a threshold photoionization mass spectrometer.

Endpoint detection by chemical reaction

A process of etching an oxide layer placed over a nitride layer of a substrate with high selectivity. The process comprises plasma etching the oxide layer of the substrate with a carbon and fluorine-containing gas and with a nitrogen-containing gas. A Si,N,species is formed which is deposited on the nitride layer substantially in equilibrium with etching of the nitride layer.

Selective dry etch of a dielectric film

Detection of the endpoint for removal of a target film overlying a stopping film by removing the target film with a process that selectively generates a chemical reaction product (for example ammonia when polishing a wafer with a nitride film in a slurry containing KOH) with either the target or stopping film, and monitoring the level of chemical reaction product by threshold photoionization mass spectroscopy as the target film is removed.

Endpoint detection by chemical reaction and photoionization

Detection of the endpoint for removal of a target film overlying a stopping film by removing the target film with a process that selectively generates a chemical reaction product (for example ammonia when polishing a wafer with a nitride film in a slurry containing KOH) with either the target or stopping film, and monitoring the level of chemical reaction product as the target film is removed. Also, detection of a substance at very low concentrations in a liquid, by extracting the substance present as a gas from the liquid and monitoring the gas to detect the substance.

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Highland Mills, NY, United States of America

Chienfan Yu