Faraday Technology Corporation

Chien-Yuan Pao

Jin-Fu Li

Tsu-Wei Tseng

Chih-Chiang Hsu

Yu-Jen Huang

Chun-Hsien Wu

A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault ('fault memory' for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.

Built-in redundancy analyzer and method for redundancy analysis

A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.

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Taipei, Taiwan

Chien-Yuan Pao