United Microelectronics Corp.

Chien-Wen Yu

Huan-Chi Ma

Ti-Bin Chen

Shao-Ping Chen

Chih-Chiang Wu

Tsai-Yu Wen

Ching-I Li

Shi-You Liu

Ya-Yin Hsiao

Yu-Chun Liu

Nien-Ting Ho

Shih-Min Chou

Hui-Hsin Hsu

Cheng-Guo Chen

Ta-Kang Lo

Kuo-Chin Hung

Kuo-Yu Liao

Kuan-Ting Lin

Ying Jie Huang

Kuan-Ting Lu

Wei-Da Lin

Yi-Chuan Chen

Jian-Li Lin

Huan Chi Ma

Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.

Semiconductor device and method of forming the same

A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

MOS capacitor and fabrication method thereof

A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Semiconductor device and manufacturing method thereof

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

P-type field effect transistor and method for fabricating the same

A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.

A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

P-type field effect transistor having channel region with top portion and bottom portion

A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.

Growing community of inventors

Kaohsiung, Taiwan

Chien-Wen Yu