Powertech Technology Inc.

Radiant Innovation Inc.

Chien-Wen Huang

Li-Chih Fang

Ji-Cheng Lin

Chun-Te Lin

Yung-Chang Chang

Che-Min Chu

Feng-Lien Huang

Yi-Chun Tsai

Wen-Jeng Fan

Ming-Hung Chang

Chia-Wei Chiang

Po-Hung Chen

A temperature calibration method of an infrared thermal image camera and a calibration method of a temperature sensing system of an infrared thermal image camera are provided. The temperature calibration method of the infrared thermal image camera includes: providing a temperature sensing system to measure an object under test, so as to obtain an uncalibrated temperature; and calibrating the uncalibrated temperature to obtain a calibrated temperature, according to the uncalibrated temperature and a temperature calibration function. The temperature calibration function is obtained through a regression analysis.

Temperature calibration method of infrared thermal image camera and calibration method of temperature sensing system of infrared thermal image camera

A temperature calibration method includes providing a temperature measuring device including a movable shutter module, and a first and a second non-contacting temperature sensing module, and a movable shutter structure of the movable shutter module includes a black substance for generating a predetermined heating temperature; moving the movable shutter structure to a first position by driving of the electric control driver, so as to completely block a first temperature-measuring viewing angle of the first non-contacting temperature sensing module and a second temperature-measuring viewing angle of the second non-contacting temperature sensing module by the black substance; measuring the predetermined heating temperature that is generated by the black substance by the second non-contacting temperature sensing module at the second temperature-measuring viewing angle so as to obtain black body temperature information of the black substance; and calibrating the first non-contacting temperature sensing module according to the black body temperature information.

Temperature calibration method for a temperature measuring device

A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

Stacked chip package structure and manufacturing method thereof

A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Semiconductor package and manufacturing method thereof

A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection structures between the main substrate and the carrier substrate. The shielding layer covers the top surface and the sidewalls of the molding compound and a portion of the carrier substrate. The shielding layer is electrically grounded through the connection structures.

Growing community of inventors

Hsinchu County, Taiwan

Chien-Wen Huang