Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Other

Global Unichip Corporation

Au Optronics Corporation

Acer Inc.

Wistron Corporation

Opto Plus Led Corp.

Chien-Wen Chen

Mu-Jen Huang

Yu-Sian Jiang

Heng-Kai Liu

Clement Hsingjen Wann

Kong-Beng Thei

Yung-Chow Peng

Chih-Sheng Chang

Harry Chuang

Yi-Tang Lin

Wei-Ting Lin

Chin-Shen Lin

Ke-Ying Su

Tsung-Hsin Yu

Cheok-Kei Lei

Shih-Kai Lin

Chia-Ming Ho

Ming-Jer Chiu

Ming-Hui Tung

Hsiao-Hui Chen

Cheng-Chi Wu

Rachid Salik

Shu-Yu Chen

Chih-Tsung Yao

Chih Chi Hsiao

Yu-Ning Chang

Wen-Ju Preet Yang

Chin-Chang Hsu

Ching-Chi Lin

Gwan Sin Chang

Chia-Jen Kao

Hsien Yu-Tseng

Louis Chao-Chiuan Liu

Chen-Fa Tsai

Tsung-Yen Liu

Chauchin Su

Ting-Wei Hsu

Hsien-Yu Tseng

Harry-Hak-Lay Chuang

Hsin-Yi Lee

Chen-Hsien Liao

Chien-Huang Liao

Jenn-Jia Su

Kun-Sheng Chang

Yi-Ting Lin

Shih-Ting Huang

Meng-Chun Chang

Chao-Wei Yeh

Ya-Li Tai

Gwan-Sin Chang

Leaf Chen

An-Ming Lee

Chien-Cheng Chen

Chung-Chang Lin

Ming-Ching Yen

Chuan-Chun Wang

Kai-Chieh Yang

Chun-Ming Chou

Longqiang Zu

Yu-Tai Chia

Chung-Shi Chiang

Guan-Yu Chen

Heng Kai Liu

Victor C Y Chang

Yi-Ching Liao

Chih-Yu Chen

Yi-Fan Tsai

Hong-Gi Wei

Chen-Chen Ou Yang

Chuan-Yuan Li

Jui-Cheng Chuang

Meng-Huan Yang

Hung-Shiang Ruan

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Integrated circuit layout validation using machine learning

A feed forward echo cancellation device includes a first impedance circuit, a second impedance circuit, and an echo cancellation current generator circuit. The first impedance circuit is configured to output a first current to a node in response to a transmission current. The second impedance circuit is configured to output a second current to a node in response to the transmission current. The echo cancellation current generator circuit is configured to drain an echo cancellation current from the node. The node is connected to an input terminal of a programmable gain amplifier circuit via a gain control circuit, and the gain control circuit is configured to set a gain of the programmable gain amplifier circuit.

Feed forward echo cancellation device and echo cancellation method

A feedforward echo cancellation device includes: a first impedance circuit for responding to a transmission current to output a first current to a node; an echo cancellation current generating circuit for drawing an echo cancellation current from the node; a circuit module that is coupled to the echo cancellation current generating circuit and the node has a first impedance value adjusted based on a system convergence index of a communication device, where the first impedance value is used to determine a gain of a programmable gain amplifier in the communication device; and a second impedance circuit for responding to the transmission current to output a second current to the node, where a second impedance value of the second impedance circuit is adjusted based on the first impedance value of the circuit module accordingly. Specifically, the node is coupled to an input terminal of the programmable gain amplifier.

Feedforward echo cancellation device

A touch display device includes a printed circuit board and a cover. The printed circuit board has a top surface, a bottom surface and soldering points. The printed circuit board includes a first printed circuit, a light element and a second printed circuit. A part of the first printed circuit is on the top surface or the bottom surface and connected with the corresponding soldering point. The light emitting element is on the top surface and electrically connected to the first printed circuit. On the top surface, the second printed circuit does not overlap with the first printed circuit. The cover covers the printed circuit board. The cover has light transmission areas which are aligned with the light elements. The second printed circuit is configured to provide a capacitance value coupled to a capacitive sensing element coupled between the second printed circuit and the cover.

Touch display device and touch display module

A motor driving device includes a first hysteresis comparator, a second hysteresis comparator, a logic circuit, a control unit, and an inverter circuit. The logic circuit receives a start signal or a start completion signal to output the first output signal as a commutation signal according to the start signal, or to output the second output signal as the commutation signal according to the start completion signal, clamps the second output signal by the first output signal, stops outputting the commutation signal after the potential state of the commutation signal is changed, and unclamps the second output signal with the first output signal and outputs the commutation signal in response to a difference voltage between the first input signal and the second input signal being greater than a positive value of the first hysteresis voltage or less than a negative value of the first hysteresis voltage.

Phase-locked loop circuit

A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

Delay circuit

A phase-locked loop circuit includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay phase-locked loop phase locks a first reference clock and a second reference clock to an input clock, and includes a phase correction circuit, an integrator, a first sub-sampling phase detector, and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output clock with a predetermined phase-locked loop frequency, and the output clock is phase-locked to the first reference clock, the sub-sampling phase-locked loop includes a second sub-sampling phase detector, a second charge pump, a phase frequency detecting circuit, a voltage controlled oscillator and a first frequency divider. The first sub-sampling phase detector and the second sub-sampling phase detector have a symmetric circuit structure, and a first charge pump circuit and a second charge pump circuit have a symmetric circuit structure.

A back cover includes a metal body having a first side, a second side, and a groove that is formed at the first side. The metal body further has a first radiator, a second radiator, and a ground radiator. The first radiator is disposed in the groove, and has a main portion and a support portion that cooperatively form a T-shape. The main portion includes a feeding end adjacent to a closed end of the groove. The second radiator is adjacently connected to the groove and is defined by the first and second sides, and an edge of the groove. The ground radiator is formed by a portion of the metal body excluding the first and second radiators. The second radiator and the support portion are connected to the ground radiator. The first and second radiators, and the ground radiator are serve as an antenna structure.

Back cover for electronic device and electronic device

Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.

Clock adjustment circuit and clock adjustment method

The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.

Circuit capable of protecting low-voltage devices

A mobile device includes a metal mechanism element, a ground plane, a feeding element, a parasitic element, and a dielectric substrate. The metal mechanism element has a slot. The ground plane is coupled to the metal mechanism element. The feeding element is coupled to a signal source. The feeding element extends across the slot. The parasitic element is coupled to the ground plane. The parasitic element extends across the slot. The ground plane, the feeding element, and the parasitic element are disposed on the dielectric substrate. An antenna structure is formed by the feeding element, the parasitic element, and the slot of the metal mechanism element.

Mobile device

A combo chip is provided. The combo chip is applicable to an USB connector, and includes an USB type-C circuit, an USB non-type-C circuit, a switch unit, and a mode control unit. The switch unit is connected to the USB type-C circuit and the USB non-type-C circuit, and the mode control unit is connected to a control terminal of the switch unit. After performing one or more mode determination procedures, the mode control unit controls the switch unit to connect the USB type-C circuit to a first pin and a second pin while disconnecting the USB non-type-C circuit from the first pin and the second pin, or otherwise controls the switch unit to connect the USB non-type-C circuit to the first pin and the second pin while disconnecting the USB type-C circuit from the first pin and the second pin.

Combo chip for USB connector

A control method, which is adapted to a phase interpolator configured to generate an output signal based on a current distribution ratio, includes following operations: selecting a first input pair and a second input pair from the phase interpolator; sequentially switching currents associated with the current distribution ratio from the first input pair to flowing through the second input pair, in order to adjust a phase of the output signal to correspond to a first phase interval; and after all of the currents flow through to the second input pair, selecting the second input pair and a third input pair from the phase interpolator, and adjusting the current distribution ratio to correspond the phase of the output signal to a second phase interval, in which the first phase interval and the second phase interval are continuous.

Phase adjustment circuit, control method, and measurement method

Growing community of inventors

Hsinchu, Taiwan

Chien-Wen Chen