Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Chien-Wei Tseng

Ming-Da Tsai

Bernard Mark Tenbroek

Chien-Cheng Lin

Yangjian Chen

Ian Tseng

Li-Shin Lai

Mohammed Fathey Abdelfattah Hassan

Tzu-Yu Yeh

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

Phase synchronized LO generation

A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45&#xb0; phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45&#xb0; phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

Quadrature transmitter, wireless communication unit, and method for spur suppression

A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

Phase-rotated harmonic-rejection mixer apparatus

A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.

Power amplifier system and associated bias circuit

A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.

Power amplifier system and associated control circuit and control method

A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path. The first set of quadrature signals is a substantially 45&#xb0; phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45&#xb0; phase shifted version of the second set of quadrature LO signals.

Growing community of inventors

Keelung, Taiwan

Chien-Wei Tseng