Mediatek Corporation

Chien-Wei Lin

Kai-Chun Lin

Chi-Hung Chen

Meng-Jye Hu

Chih-Wen Yang

Hsiao-En Chen

A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

Prediction processing system using reference data buffer to achieve parallel non-inter and inter prediction and associated prediction processing method

A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

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Hsinchu, Taiwan

Chien-Wei Lin