Richtek Technology Corporation

Vanguard International Semiconductor Corporation

Richtek Technology Corporation, R.o.c

Chien-Wei Chiu

Tsung-Yi Huang

Chien-Yu Chen

Chih-Fang Huang

Ting-Fu Chang

Ting-Wei Liao

Kun-Huang Yu

Tsung-Yu Yang

Tsung-Chieh Hsiao

Wu-Te Weng

Ya-Hsien Liu

Po-Chin Peng

Shin-Cheng Lin

Hung-Der Su

Ta-Yung Yang

Kuo-Chin Chiu

Chih-Wen Hsiung

Yung-Hao Lin

Chien-Hsien Song

Chien-Hao Huang

Yong-Zhong Hu

Chun-Lung Chang

Yu-Hao Ho

Li-Che Chen

Hsing-Chao Liu

Chu-Feng Chen

Kuo-Hsuan Lo

Wei-Chun Chou

Ying-Kai Chou

K C Chang

Chun-Fu Liu

Ching-Jong Chen

Fan Ho

Huang-Ping Chu

Chien-Kai Chang

A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

High voltage device and manufacturing method thereof

A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

Power device and manufacturing method thereof

A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Switching converter circuit and driver circuit having adaptive dead time thereof

A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

Switch capable of decreasing parasitic inductance

A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.

Semiconductor devices and methods for manufacturing the same

A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.

Semiconductor device and method for manufacturing the same

Embodiments of the disclosure relate to an enhanced-mode high electron mobility transistor. The enhanced-mode high electron mobility transistor includes a substrate, a first III-V semiconductor layer disposed on the substrate, a second III-V semiconductor layer disposed on the first III-V semiconductor layer, a third III-V semiconductor layer disposed on the second III-V semiconductor layer, an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer to serve as an isolation region, and a gate electrode disposed in the amorphous region. The second III-V semiconductor layer and the third III-V semiconductor layer include different materials to form a heterojunction.

Enhanced-mode high electron mobility transistor and method for forming the same

A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer formed thereon. The method also includes forming an insulating material layer on the semiconductor substrate, wherein the semiconductor substrate and the first gate structure are covered by the insulating material layer. The method further includes removing a portion of the insulating material layer in a high-voltage element region to form a second gate dielectric layer in the high-voltage element region on the semiconductor substrate, and forming a second gate electrode layer on the second gate dielectric layer.

A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the first gallium nitride layer has a dopant concentration which is greater than that of the second gallium nitride layer. The semiconductor device further includes an anode electrode disposed on the second gallium nitride layer, a cathode electrode disposed on and in direct contact with the first gallium nitride layer, and an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.

High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate and an isolation structure in the substrate. The high-voltage semiconductor device includes a gate structure disposed on the substrate, wherein the gate structure is separated from the isolation structure by a distance. The high-voltage semiconductor device also includes a metal electrode disposed on the gate structure, wherein the metal electrode extends to directly above the isolation structure. The high-voltage semiconductor device further includes an interconnection structure including the lowest metal layer, wherein the metal electrode is between the lowest metal layer and the gate structure. Methods of manufacturing the high-voltage semiconductor device are also provided.

High-voltage semiconductor device and method of manufacturing the same

A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.

The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

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Yunlin, Taiwan

Chien-Wei Chiu