Mediatek Corporation

Macronix International Co., Ltd.

Realtek Semiconductor Inc.

Au Optronics Corporation

Chien-Wei Chen

Yu-Li Hsueh

Yao-Chi Wang

Keng-Meng Chang

Jiun-Ren Lai

Chao-Ching Hung

Sen-You Liu

Tsung-Han Li

You-Wen Chiou

Bo Yu Lai

Kuan-Chi Chou

Ming-Chung Liang

Wei-Hung Kuo

Po-Chun Huang

Shin-Yi Tsai

Shih-Po Chou

Cheng-Hsing Lin

Wen-Ching Sung

Yu-Ying Tang

Kairen Fong

A media docking device is provided and includes an input module, an output module, and a process module. The input module is electrically connected to a media source device. The output module is electrically connected to multiple media playing devices and obtains device data from the media playing devices. The process module transmits the device data and screen numbers to the media source device through the input module. When determining to perform a display switch procedure, the process module modifies the device data and the screen numbers, and transmits the modified device data and the modified screen numbers to the media source device through the input module. The process module also transmits media data from the media source device to the corresponding media playing device.

Media docking device and media docking method

A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Media docking device and media transfer method

A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.

Frequency calibration circuit and method for calibrating oscillation frequency of controllable oscillator

A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Crystal oscillator and method for performing startup of crystal oscillator

A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Frequency-locked loop and method for correcting oscillation frequency of output signal of frequency-locked loop

A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Crystal oscillator and phase noise reduction method thereof

A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

Method for startup of crystal oscillator with aid of external clock injection, associated crystal oscillator and monitoring circuit therein

The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Clock buffer having low power, low noise and low spur

A display device includes a substrate, a light shielding layer, at least one fading pattern and a display module. The display module is disposed on the substrate and has a display area. The light shielding layer is disposed on a periphery of the substrate and has a first side and a second side, wherein the first side is opposite to the second side. The at least one fading pattern is disposed on the substrate, is adjacent to at least one side of the first side and the second side of the light shielding layer, and does not overlap the display area of the display module. Each fading pattern includes N light transmissible areas, the N light transmissible areas are adjacent to each other, and transmittances of the N light transmissible areas are different from each other, wherein N is a positive integer larger than one.

Display device

Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

Pitch reduction integrating formation of memory array and peripheral circuitry

A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.

Method for forming an electrical insulating layer on bit lines of the flash memory

Nonvolatile memory devices, such as NROM devices that have an oxide-nitride-oxide (ONO) layer beneath at least one word line structure, and methods for making same, are disclosed. The ONO layer is formed on a substrate, followed by a patterned photoresist layer being formed on the ONO layer. The patterned photoresist layer then serves as an implanting mask to form at least one bit line in the substrate, followed by a material layer being formed on the substrate. The material layer is planarized until the photoresist layer is exposed, and the photoresist layer is then removed. A polymer layer is formed, using a dielectric resolution enhancement coating technique, on exposed surfaces of the material layer, with the polymer layer serving as an etching mask to define the top oxide layer and the nitride layer of the ONO layer. The polymer layer and the material layer are then removed.

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Hsinchu, Taiwan

Chien-Wei Chen