United Microelectronics Corp.

Industrial Technology Research Institute

Chien-Ting Lin

Shih-Hung Tsai

Ssu-I Fu

Che-Hua Hsu

Li-Wei Cheng

Guang-Hwa Ma

Chien-Ming Lai

Yi-Wen Chen

Ying-Tsung Chen

Yu-Ping Wang

Po-Chao Tsao

Wen-Tai Chiang

Chun-Hsien Lin

Shih-Fang Tzou

Yi-Hui Lee

Ying-Cheng Liu

Cheng-Hsien Chou

I-Ming Tseng

Chih-Hao Yu

Hui-Lin Wang

Yu-Hsiang Hung

Chen-Yi Weng

Jing-Yin Jhang

Chin-Yang Hsieh

Chung-Fu Chang

Yi-An Shih

Cheng-Guo Chen

Li-Wei Feng

Jyh-Shyang Jenq

Chih-Wei Chen

Shao-Hua Hsu

Yi-Wei Chen

Chih-Sen Huang

Po-Jui Liao

Chan-Lon Yang

Chih-Kai Hsu

Jiunn-Hsiung Liao

Teng-Chun Tsai

Ching-Wen Hung

Chin-Fu Lin

Chi-Mao Hsu

Yu-Tsung Lai

Chao-Hung Lin

Ching-Ling Lin

Shin-Chi Chen

Tong-Jyun Huang

Feng-Yi Chang

Chin-Cheng Chien

Chun-Yuan Wu

Yu-Hsiang Lin

Chun-Lung Chen

Chin-Hung Chen

Chia-Jung Hsu

Jia-Rong Wu

Kun-Yuan Liao

Chia-Lin Lu

Chun-Ya Chiu

Yen-Liang Wu

Chia-Wen Liang

Hung-Chan Lin

Chia-Jui Liang

Yu-Cheng Tung

Chih-Chien Liu

Chia-Lin Hsu

Hua-Chou Tseng

An-Chi Liu

Rai-Min Huang

Chang-Tzu Wang

Zhi-Cheng Lee

Chien-Liang Lin

Po-Cheng Huang

Hsuan-Hsu Chen

Hsiao-Pang Chou

Chih-Yu Tseng

Ying-Chih Lin

Wei-Tsun Shiau

Jie-Ning Yang

Mei-Ling Chao

Ching-Yu Chang

Chieh-Te Chen

Chih-Sheng Chang

Hsin-Yu Chen

Hsin-Fu Huang

Wen-Han Hung

Shui-Yen Lu

Jiunn-Ren Hwang

Shou-Wei Hsieh

Pei-Yu Chou

Chin-Sheng Yang

Min-Chuan Tsai

Shih-Fang Hong

Chiu-Hsien Yeh

Yu-Ting Li

Chun-Hao Lin

Chia-Jong Liu

Chen-Hua Tsai

Ming-Te Wei

Lung-En Kuo

Ching-Li Yang

Shao-Wei Wang

A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Semiconductor structure including seal ring structure

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.

Semiconductor device and method for fabricating the same

A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Semiconductor structure and method for forming the same

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Method for integrating high-voltage (HV) device, medium-voltage (MV) device, and low-voltage (LV) device

A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Magnetoresistive random access memory and method of manufacturing the same

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.

A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

MRAM semiconductor structure and method of forming the same

A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

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Hsinchu, Taiwan

Chien-Ting Lin