Wintek Corporation

Dongguan Masstop Liquid Crystal Display Co., Ltd.

Industrial Technology Research Institute

Chien-Ting Chan

Wen-Chun Wang

Hsi-Rong Han

Kuo-Chang Su

Yi-Cheng Tsai

Chin-Chang Liu

Wei-Yuan Cheng

Kuo-Lung Lo

Chih-Yuan Wang

Wan-Jen Tsai

Yi-Chin Wang

Ying-Cheng Tsai

A shift register including a plurality of multi-stage shift register circuits is provided. The mstage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mperiod, is defined on the node. The shift register unit is controlled by an (m&#x2212;1)stage output signal provided by an (m&#x2212;1)stage shift register circuit and a clock signal for providing the enabled mstage output signal in the mperiod, and controlled by an (m+1)stage second control signal provided by an (m+1)stage shift register circuit for providing a disenabled mstage output signal in the (m+1)period. The control circuit, controlled by the clock signal, provides and outputs an mstage second control signal to the (m&#x2212;1)stage shift register circuit according to the mstage first control signal, wherein m is a natural number greater than 1.

Shift register and gate driver with compensation control

A shift register includes multiple stages each generating a scan signal at an output terminal and including a level pull-up circuit, a level pull-down circuit, a driving circuit and a level controlling circuit. The level pull-up circuit makes the scan signal equal a first clock signal in response to an enabled level of a first control signal. The level pull-down circuit makes the scan signal equal a first voltage in response to an enabled level of a second control signal. The driving circuit controls the first control signal to be the enabled level and a disabled level in response to an enabled level of an input signal and the enabled level of the second control signal, respectively. The level controlling circuit controls the second control signal to be the disabled level and the enabled level in response to the enabled level and the disabled level of the input signal, respectively.

Shift register

A pixel structure including a scan line, a data line intersecting the scan line, a first gate, a second gate, a third gate, a semiconductor layer, a source, a first drain, a second drain, a first pixel electrode, and a second pixel electrode is provided. The dataline and the scan line are interlaced disposed. The semiconductor layer is disposed on the scan line to define the first gate and the second gate. The source is directly connected to the data line and located between the first gate and the second gate. The first gate is located between the first drain and the source. The second gate is located between the second drain and the source. The third gate is electrically connected to the scan line. The first pixel electrode and the second pixel electrode are respectively electrically connected to the first drain and the second drain.

Pixel structure

A demultiplexer drive circuit includes a first, a second, a third, a fourth, and a fifth switching devices. The first switching device is connected to the first and the second scan clock signals. The control terminal of the second switching device is connected to the first switching device, and the rest of its terminals are connected to the data line and a first pixel electrode. The control terminal of the third switching device is connected to the first switching device, and the rest of its terminals are connected to the data line and a second pixel electrode. The fourth switching device is connected to the first and the second scan clock signals and its control terminal is connected to the third switching device. The control terminal of the fifth switching device is connected to the fourth switching device, and the rest of its terminals are connected to the data line and a third pixel electrode. The first scan clock signal and the second scan clock signal have a substantially identical pulse width and a phase difference of substantially half of the pulse width.

Demultiplexer drive circuit

An electrowetting pixel structure includes a substrate, a hydrophobic dielectric layer, a non-polar liquid, a polar liquid, at least one electrode, and at least one contact hole. The hydrophobic dielectric layer is formed on the substrate, the non-polar liquid covers one surface of the hydrophobic dielectric layer, and the polar liquid is provided on the hydrophobic dielectric layer where the non-polar liquid and the polar liquid are immiscible. The electrode is formed on the substrate and divides the substrate into an electrode section and a non-electrode section. When a voltage is applied to the electrowetting pixel structure, the non-polar liquid contracts on the hydrophobic dielectric layer and is confined to an area substantially overlapping the non-electrode section. The contact hole is formed on the substrate at a position away from the non-electrode section of the electrowetting pixel structure.

Electrowetting pixel structure

A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.

A pixel unit includes a first control circuit and a second control circuit and is divided into a first region and a second region. The first control circuit determines the output voltage of the first region and includes a first switching device, a first liquid crystal capacitor and a first storage capacitor coupled to the first switching device. The second control circuit determines the output voltage of the second region and includes a second switching device, a second liquid crystal capacitor and an auxiliary capacitor coupled to the second switching device, and a third switching device. The third switching device is coupled to the second switching device through the auxiliary capacitor, and the output voltage of the first region is different to that of the second region.

Liquid crystal display and pixel unit thereof

A photosensor for a display device includes a light receiver, a reset unit, and a sample unit. The light receiver is used for receiving ambient light to generate a photovoltage. The light receiver includes a first transistor and a first conversion unit that transforms the output of the first transistor into the photovoltage. The reset unit is used for providing an initiated reference voltage in response to a reset signal and includes a second transistor and a third transistor that are connected with each other, where the first conversion unit is discharged through the third transistor to obtain the initiated reference voltage when the second transistor is turned on. The sample unit is used for outputting the photovoltage in respond to a sample signal, the sample unit comprising a fourth transistor in respond to the sample signal and a second conversion unit that transforms the output of the fourth transistor into the photovoltage.

Photosensor for display device

A shift register has shift register units. The nshift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage to an output terminal. The first driving unit and the first level control unit are coupled to a first node, and a voltage on the first node is a first control signal. The first driving unit turns on and off the first level control unit in response to an input signal and second and third control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output terminal in response to a front edge of the first control signal of the (n+2)shift register unit.

Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof

A bi-directional shift register includes N stages, wherein the mstage among the N stages includes a node, an output end, first input circuit, second input circuit, and a shift register unit. N is a natural number greater than 1 and m is a natural number smaller than or equal to N. First control signal is measured on the node. The output end outputs an moutput signal. The first input circuit receives an m&#x2212;1output signal as a control signal and a power signal to accordingly generate an enabled first driving signal to the node in first period. The second input circuit receives an m+1output signal as a control signal and a power signal to accordingly generate an enabled second driving signal to the node in second period. Controlled by the first control signal, the shift register unit generates an moutput signal in third period.

Bidirectional shift register

A level shifting circuit including a driving circuit, a reset circuit, a coupling circuit and an output-stage circuit is provided. The driving circuit, controlled by the input signal, controls the first driving signal having a high voltage level in the first period and controls the first driving signal having a low reference level in the second period. The reset circuit, controlled by the first driving signal in the first period, resets the second driving signal having the low reference level. The coupling circuit, controlled by the falling edge of the input-inversed signal, controls the second driving signal having a low voltage coupling level in the second period. The output-stage circuit, controlled by the first and the second driving signal, controls the output signal having a high voltage level in the second period and controls the output signal having a low voltage level in the first period.

Level shifting circuit

A shift register is for generating scan signals. Each stage of the shift register comprises a first level lifting unit and at least a second level lifting unit, a first level lowering unit and at least a second level lowering unit, first and second driving units. The first level lowering and lifting units are for controlling the levels of signals at the first output terminal to output a first scan signal. The second level lowering unit and second level lifting unit are for controlling the levels of signals at the second output terminal to output at least a second scan signal. The first and second driving units are for turning on and off the first and the second level lifting units and the first and the second level lowering unit to control the first and second scan signals.

Shift register and liquid crystal display

A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.

Shift register and level controller

A multi-domain liquid crystal display includes a plurality of first and second picture elements having polarities opposite to each other under the same frame of an inversion drive scheme. Each first picture element has an extension part positioned next to at least one side of the adjacent second picture element, and each second picture element has an extension part positioned next to at least one side of the adjacent first picture element.

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Changhua County, Taiwan

Chien-Ting Chan