Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Chien-Te Tu

Chee-Wee Liu

Yu-Shiang Huang

Yi-Chun Liu

Fang-Liang Lu

Chung-En Tsai

Chia-Che Chung

Hung-Yu Yeh

Hsin-Cheng Lin

Hung-Yu Ye

A method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of sacrificial layers and a plurality of channel layers alternately arranged over the semiconductor substrate, and each of the sacrificial layers is a multi-layer film comprising a bottom epitaxial layer, a middle epitaxial layer over the bottom epitaxial layer, and a top epitaxial layer over the middle epitaxial layer, wherein the middle epitaxial layer has a lower germanium concentration than the bottom and top epitaxial layers; laterally recessing the sacrificial layers to form sidewall recesses alternating with the channel layers; forming inner spacers in the sidewall recesses; forming source/drain epitaxial structures on opposite sides of the channel layers.

Semiconductor device and manufacturing method thereof

A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.

Fin field effect transistors (FINFET) device including a plurality of recessed regions alternating with unrecessed regions in channel stack

The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Gate-all-around transistor with strained channels

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Stacked semiconductor device with nanostructure channels

Stacked semiconductor device with nanostructure channels and manufacturing method thereof

A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Semiconductor device and formation method

A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Gate-all-around device

The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.

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Chien-Te Tu