Siliconware Precision Industries Co., Ltd.

Sandisk Technologies Inc.

Chien-Te Chen

Chien-Ping Huang

Chih-Chin Liao

Yu-Po Wang

Tzong-Da Ho

Binbin Zheng

Wen-Jung Chiang

Hsiang Ju Huang

Yu-Lin Liao

Cheng-Hsiung Yang

Songtao Lu

Chih-Hao Chang

In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

Printed circuit board having a sacrificial pad to mitigate galvanic corrosion

Socket wrench

A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

Circuit board with quality-indicator mark and method for indicating quality of the circuit board

A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

High electrical performance semiconductor package

A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between the adjacent substrate units and electrically connected to the circuit structures, and a molding ring surrounding all the substrate units. The molding ring is located at a position predetermined for contacting the substrate with a mold. A solder mask layer covers the circuit structures, the plating buses and the molding ring, and is formed with a plurality of openings therein, such that predetermined portions of the circuit structures are exposed via the openings and serve as electrical input/output connections. During a molding process, the mold can tightly abut against the solder mask layer covering the molding ring to prevent outward flashes of an encapsulating material.

Flash preventing substrate and method for fabricating the same

A chip carrier for testing electrical performance of a passive component includes: a core layer having a plurality of conductive traces on a surface thereof; at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger on the surface of the chip carrier and to a first ball pad on an opposite surface of the chip carrier; at least one second trace not connected with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, one end of the second trace being electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces, with the first and second predetermined positions exposed.

Chip carrier and method for testing electrical performance of passive component

A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.

Substrate for accommodating passive component

A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging. Further, the toothed portions of the power ring and the ground ring are large in area, whereby two or more power vias or ground vias can be gathered together to increase the overall electrical performance, and whereby the packaged chip can be increased in heat-dissipation efficiency.

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Taichung, Taiwan

Chien-Te Chen