Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Tai Chan

Chun Hsiung Tsai

Da-Wen Lin

Kei-Wei Chen

Ziwei Fang

Hsien-Chin Lin

Wei-Yang Lee

Huai-Tei Yang

Chia-Pin Lin

Su-Hao Liu

King-Yuen Wong

Wei-Yuan Lu

Chun-Hsiung Tsai

Kuo-Feng Yu

Hung-Kai Chen

Li-Wen Weng

Huicheng Chang

Tung Ying Lee

Chung-Cheng Wu

Chien-Chang Su

Shyue-Shyh Lin

Yee-Chia Yeo

Szu-Ying Chen

Liang-Yin Chen

Ka-Hing Fung

Kuang-Yuan Hsu

Yuan-Ching Peng

Hsien-Hsin Lin

Chun-Fu Cheng

Ting-Yeh Chen

Chien-Chih Lin

Chia-Ling Chan

Ming-Lung Cheng

Shih-Syuan Huang

Han-Pin Chung

Tsung-Hung Lee

Mao-Rong Yeh

Yu-Lien Huang

Chun-Feng Nieh

Tsan-Chun Wang

Chang-Miao Liu

De-Wei Yu

Xusheng Wu

Wen-Sheh Huang

Wei-Ken Lin

An-Shen Chang

Bwo-Ning Chen

Yin Wang

Hsueh-Jen Yang

Yu-Ching Huang

Chun-Te Li

Chih-Hung Tseng

A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.

Structure and formation method of semiconductor device with epitaxial structures

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Variable size fin structures

A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Semiconductor device structure and method for forming the same

A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cmwithin a depth range of about 0-5 nm from a surface of the strained layer.

Method of forming semiconductor device

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Formation of dislocations in source and drain regions of FinFET devices

A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

Gate structure, semiconductor device and the method of forming semiconductor device

Formation of dislocations in source and drain regions of finFET devices

Semiconductor device and FinFET device

A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Method of making a FinFET, and FinFET formed by the method

A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Fin field-effect transistor structure and method for forming the same

A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.

Fin field effect transistor and method for fabricating the same

Method of making a finFET, and finFET formed by the method

Growing community of inventors

Hsinchu, Taiwan

Chien-Tai Chan