Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Guardian Corp.

Agere Systems Inc.

Alcatel-lucent USA Inc.

Alcatel Lucent

Chien-Shing Pai

Wei Zhu

Stanley K Pau

Pang-Dow Foo

Sungho Jin

Vladimir Anatolyevich Aksyuk

Nagesh R Basavanhally

Omar Daniel Lopez

Ruichen Liu

Chorng-Ping Chang

Joseph Ashley Taylor

Chun-Ting Liu

Flavio Pardo

Shu Yang

Elsa Reichmanis

William T Lynch

Omkaram Nalamasu

Ajit S Manocha

Kin Ping Cheung

Kwok K Ng

John F Miner

Yih-Cheng Shih

The present invention provides an apparatus. The apparatus, in one embodiment, includes an actuator located over a substrate, a movable feature located over and coupled to the actuator, and a layer of material located above the actuator and movable feature and not constituting part of a beam/spring associated with the movable feature, the layer of material configured as a reservoir having an interior capable of holding a liquid, the movable feature being exposed to the interior.

Apparatus having a layer of material configured as a reservoir having an interior capable of holding a liquid

The present invention provides a process for manufacturing an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer of material located over the actuator, movable feature and sacrificial material. The process may further include removing only a portion of the layer of material to expose the sacrificial material, and subjecting the exposed sacrificial material to an etchant to release the movable feature.

Process for manufacturing an apparatus that protects features during the removal of sacrificial materials

A chemical reactor includes two substrates that are joined along a surface and a chemical reaction chamber formed between the substrates. The chemical reaction chamber has a hollow interior and one or more light reflectors located along walls of the hollow interior. The chemical reaction chamber has one or more inputs to transport fluid into the hollow interior and an output to transport fluid out of the hollow interior. The one or more light reflectors cause light rays to make multiple crossings of the hollow interior as a result of reflections off the one or more reflectors.

Light-mediated micro-chemical reactors

An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.

Wafer-based ion traps

An apparatus includes a semiconductor or dielectric wafer-substrate and first and second multi-layer structures located over the wafer-substrate. The first multi-layer structure includes an ionizer or an electronic ion detector. The second multi-layer structure includes an ion trap having entrance and exit ports. The ionizer or electronic ion detector has a port coupled to one of the ports of the ion trap.

Mass spectrometers on wafer-substrates

A process for fabricating an integrated semiconductor device with a low dielectric constant material and an integrated semiconductor device with the low dielectric constant material interposed between two conductors is disclosed. The low dielectric constant material has a dielectric constant of less than about 2.8. The low dielectric constant material is a porous glass material with an average pore size of less than about 10 nm. The low dielectric constant material is formed on a semiconductor substrate with circuit lines thereover by combining an uncured and unmodified glass resin with an amphiphilic block copolymer. The amphiphilic block copolymer is miscible in the uncured glass resin. The mixture is applied onto the semiconductor substrate and the glass resin is cured. The glass resin is further processed to decompose or otherwise remove residual block copolymer from the cured glass resin.

Semiconductor device having a low dielectric constant dielectric material and process for its manufacture

The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrier region and in any underlying regions deposited on the silicon, providing a trench in the silicon substrate at the opening, depositing a dielectric material such as silicon dioxide in the trench, typically planarizing the trench silicon dioxide, and subsequently performing an oxidation step. The oxidation step rounds the otherwise sharp corners of the silicon at the area where the trench silicon dioxide meets the pad oxide. The invention thereby reduces or eliminates sharp corners that contribute to leakage current.

Process for device fabrication

It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Device comprising thermally stable, low dielectric constant material

Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate

Ion beam deposition, using a carbon- and fluorine-containing source or sources, is used to form a fluorinated diamond-like carbon layer in a device, the FDLC layer exhibiting a dielectric constant of 3.0 or less along with a thermal stability of at least 400&deg; C. During the ion beam deposition, due to the unique nature of carbon chemistry, the carbon atoms combine at the substrate surface to form all possible combinations of sp,, sp,and sp,bonds. However, ion beam etching occurs along with deposition, such that atoms of the weaker carbon structures&mdash;carbyne and graphite&mdash;are removed preferentially. This leads to a buildup of a diamond-like, sp,-bonded structure with fluorine atoms, it is believed, substituted for some carbon atoms within the structure, this structure providing the desirable properties of the layer.

Article comprising fluorinated diamond-like carbon and method for fabricating article

The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

Article comprising fluorinated amorphous carbon and method for

The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, and more advantageously 2.1 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

Article comprising fluorinated amorphous carbon and process for

Integrated circuits employing titanium nitride are significantly improved by using a specific method for formation of the titanium nitride in the device fabrication. In particular, a plasma such as one formed in an electron cyclotron resonance apparatus is employed to dissociate a source of nitrogen and a source of hydrogen and the dissociation products are combined at the integrated circuit deposition substrate with titanium tetrachloride. The resulting deposition is essentially devoid of chlorine and has advantageous step-coverage properties.

Process for fabricating integrating circuits

A method of forming an interlevel dielectric suitable for use with semiconductor integrated circuits is disclosed. The dielectric illustratively includes a triple layer sandwich of ozone-TEOS formed between two layers of plasma-enhanced TEOS. The dielectric is capable of filling high-aspect ratio trenches between runners. The ozone-TEOS is formed at a high pressure (approximately 90 Torr) to reduce hydrogen absorption. The reduced-hydrogen content ozone-TEOS is less susceptible to moisture formation and, therefore, presents less risk of degrading subsequently formed aluminum runners.

Method of forming interlevel dielectric for integrated circuits

In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.

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Bridgewater, NJ, United States of America

Chien-Shing Pai