Richtek Technology Corporation

Richtek Technology Corporation, R.o.c

Chien-Sheng Chen

Shui-Mu Lin

Wei-Hsin Wei

Tsung-Wei Huang

Chin-Chiang Yeh

Chin-Tsung Chen

Jing-Meng Liu

Nien-Hui Kung

Tzu-Huan Chiu

Chien-Ping Lu

Der-Jiunn Wang

Chieh-Min Lo

The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.

Rail-to-rail comparator

A dimming method for LED driving circuit is proposed. By temporary switching a pin that is originally used for the input/output of other electric signals to a high impedance node, the dimming control signal may be inputted to dim LEDs. The dimming method comprises the steps of: floating the pin every a period of time to pull the pin's voltage being equal to the dimming control signal; detecting the pin's voltage; and retrieving the dimming control signal in accordance with the detected pin's voltage and thereafter dimming the LEDs.

Dimming method and system thereof

A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.

Tri-state output logic with zero quiescent current by one input control

Growing community of inventors

Maio-Li, Taiwan

Chien-Sheng Chen