Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien Rhone Wang

Kewei Zuo

Chih-Wei Lai

Tzu-Cheng Lin

Chung-Shi Liu

Chen-Hua Douglas Yu

Hung-Jui Kuo

Ming-Che Ho

Tzong-Hann Yang

Chia-Tung Chang

Jerry Wang

Jing-Cheng Lin

Tzu-Yu Wang

Jung Cheng Ko

Wen-Yao Chang

Yen-Hsin Liu

Y Y Peng

Chih-Chiang Chang

Tsang-Jiuh Wu

Hung-Pin Chang

Zi-Jheng Liu

Henry Lo

Ming-Tan Lee

Yu-Jen Cheng

Kuan Teng Lo

Cing He Chen

Yy Peng

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Machine learning on overlay management

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

Machine learning on overlay virtual metrology

A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

Clustering for prediction models in process control and for optimal dispatching

Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.

Near non-adaptive virtual metrology and chamber control

A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.

Die-tracing in integrated circuit manufacturing and packaging

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Adjusting sizes of connectors of package components

Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

Packaging methods, material dispensing methods and apparatuses, and automated measurement systems

A system and method is disclosed for a quality control and/or inspection procedure for assembly line processes. The disclosed system and method enable automatic optical inspection of a device during different stages of manufacture as well as in its finished form. The disclosed system and method enable the automatic quality control process to be self-learning, dynamic, and to identify and classify defects in real time.

System and method for automatic quality control for assembly line processes

The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

System and method for through silicon via yield

In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.

Solder joint reflow process for reducing packaging failure rate

A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.

Growing community of inventors

Hsin-Chu, Taiwan

Chien Rhone Wang