Via Technologies, Inc.

Chien-Ping Chung

Chung-Ching Huang

Jing-Rung Wang

Chi Hao Chang

Cheng-Wei Huang

Chung-Che Wu

Wen-Juin Huang

Yeh Cho

Lin-Hung Chen

A universal serial bus (USB) control device and a control method thereof are provided. The USB control device includes multiple host interfaces, multiple USB ports, a bus physical layer circuit, a microprocessor, and a bus schedule controller. The bus schedule controller controls the bus physical layer circuit according to a USB task. The microprocessor obtains a USB task command through the host interface, which includes a USB port number of a specific host interface. The microprocessor queries the USB port number of the specific host interface based on an index lookup table to correspond to a specific USB port, generates the USB task according to the specific USB port, and transmits the USB task to the bus schedule controller. The index lookup table is configured to record a relationship between a part of the USB port that each host interface is responsible for and the USB port number.

Universal serial bus control device and control method thereof

A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Memory access system and memory access method thereof

A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.

Computer system with adjustable data transmission rate

A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Method for accessing memory data

A bus cycle trapping system includes at least one register, a north bridge, a south bridge and a central processing unit (CPU). The register is configured to store at least one trapping parameter. The north bridge traps a bus cycle matching the at least one trapping parameter while issuing an activating signal. The south bridge sends a system management interrupt message according to the activating signal. The CPU enters a system management mode according to the system management interrupt and executes a system management interrupt routine for doing a debugging test of the bus cycle matching the trapping parameter.

System and method for trapping bus cycles

Apparatus and methods of adjusting system efficiency for a current-consuming system are disclosed. In the disclosed apparatus, a system current detector receives a system current from the current-consuming system and calculates a system current variation accordingly. A system efficiency adjustment module is coupled to the system current detector to receive the system current variation and output a frequency control signal and a voltage control signal accordingly.

Apparatus and method of adjusting system efficiency

A system and method of real-time power management for use in computer systems. The system utilization is assessed by a North bridge, and a result is transferred to a South bridge. Thereafter, through transmitting sideband signals to a voltage controller and a frequency controller by sideband pins, the North Bridge provides faster and more efficient power management performance than the system management bus (SMBUS).

System and method of real-time power management utilizing sideband pins that are dedicated to connect for transmitting sideband signal directly without software control

A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.

System and method of power management

A method and a motherboard for automatically determining the memory type. By applying the characteristics of different operational voltages for various dynamic random access memory modules, a software program is used to drive a control signal and to automatically adjust the control voltage of the dynamic random access memory. An automatic detection of the types of the dynamic random access memory is obtained. The objectives of protecting the dynamic random access memory and to allow the dynamic random access memory to operate normally can thus be achieved. The invention not only provides the detection mechanism for accessing the dynamic random access memory during the initial activation of the computer system, but also determines the voltages required by the memory module for the computer system to enter various power saving modes.

Growing community of inventors

Taipei, Taiwan

Chien-Ping Chung