Himax Technologies, Inc.

Chi Mei Optoelectronics Corporation

Hi Max Optoelectronics Corp.

Chien-Pin Chen

Lin-Kai Bu

Yen-Chen Chen

Chia-Cheng Lai

Kun-Cheng Hung

Chuan-Cheng Hsiao

Biing-Seng Wu

Hsien-Chang Tsai

Ming-Cheng Chiu

Chan-Liang Wu

Fa-Ming Chen

Sheng-Ren Chiu

Mao-Hsiung Kuo

Jang Ting Chen

Linkai Bu

A display method for driving a color-sequential display of an electronic device is provided. When the electronic device is not at low power mode, a first image is displayed first by using a second color data and a first color data of the first image sequentially to drive the display. Next, a second image is displayed by using a second color data and a third color data of the second image sequentially to drive the display. When the electronic device is at low power mode, the respective luminance of the first and the second images are obtained. Then, the respective luminance of the first image and the second image are sequentially used to drive the display.

Color-sequential display method

A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

Display device and gate driver thereof

A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.

Gate driving apparatus

The present invention relates to a driving method for cholesteric liquid crystal display. A plurality of pixels of the display are controlled by a plurality of row drivers and a plurality of column drivers. According to the method of the invention, firstly, a DC input voltage or a non-symmetric AC input voltage is applied to the row drivers and the column drivers so that the voltage of the pixel is larger than a withstand voltage of the drivers. Then, an initial column signal and an initial row signal are respectively supplied by the corresponding column driver and row driver so as to initialize the corresponding pixel. The polarity of the initial column signal is different from that of the initial row signal. Because the initial row signal minus the initial column signal equals the signal of the pixel, the amplitude of the signal applied to the pixel can be increased. Therefore, according to the invention, the initial time of the pixel can be decreased, and the transferring speed of the pixel can be improved.

Driving method for cholesteric liquid crystal display

The invention relates to a reset device for a scan driver. The scan driver is used for driving a control circuit of a display. The reset device comprises: a first input terminal, a second input terminal and a reset circuit. The first input terminal receives a first input voltage. After the first input voltage inputs to the first input terminal, the second input terminal receives a second input voltage. The second input voltage has a temporary section and a stable section. At the stable section, the second input voltage is larger than the first input voltage. When the first input terminal receives the first input voltage, the reset circuit outputs a reset signal to the scan driver. When the second input voltage is larger than a threshold value at the temporary section, the reset circuit clears the reset signal. According to the reset device of the invention, the scan driver maintains at a reset state so as to prevent that outputs of the scan driver to be at high level at the same time of supplying power. Therefore, the reset device can lower the malfunction of the control circuit and decrease the probability of damage and breakdown to maintain normal operation and life of the control circuit can be maintained.

Reset device and method for a scan driver

An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

Integrated circuit with a reduced pad bump area and the manufacturing method thereof

A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2capacitors and 2+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

High-accuracy capacitor digital-to-analog converter

A single polar driving method for a cholesteric liquid crystal display. The method comprises the steps of selecting the pixels by applying a first signal switching between a ground and a first level to the common line of the selected pixels, driving the selected pixels into a reflecting state by applying a second signal out of phase with the first signal and that switches between a second and third levels to the segment lines thereof, driving the selected pixels into a transparent state by applying a third signal in phase with the first signal and that switches between the second and third levels to the segment lines thereof, and deselecting the pixels by applying a fourth signal fixed at a fourth level to the common lines thereof.

Single polar driving method for cholesteric liquid crystal displays

An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Apparatus for switching output voltage signals

A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Growing community of inventors

Tainan, Taiwan

Chien-Pin Chen