United Microelectronics Corp.

Mediatek Corporation

Chien-Nan Lin

Kun-Ju Li

Po-Cheng Huang

Yu-Ting Li

Fu-Shou Tsai

Li-Chieh Hsu

Yi-Liang Liu

Ching-Hua Yeh

An-Li Wang

Jui-Fa Lu

You-Ming Tsao

Yu-Ting Kuo

Tsung-Shian Huang

Kuo-Yi Wang

Chi-Chiang Huang

Huei-Long Wang

Yung-Hsin Chu

Yan-Hong Zhang

An image processing method for a game loop of a game, wherein the game loop comprises a game rendering module and a MEMC module, and is executed by more than one processing unit to generate an output image to display. The image processing method includes rendering, by the game rendering module, a scene of the game to obtain a first image; rendering, by the game rendering module, a UI to obtain a second image; applying, by the MEMC module, MEMC to the first image to generate an interpolated first image; and blending, by the MEMC module, the second image and the interpolated first image into the output image.

Image processing device and image processing method for game loop

A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.

Adaptive loading-aware system management for balancing power and performance

A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

Method of dummy pattern layout

A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.

Semiconductor structure

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

Method for forming semiconductor structure

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

Method for planarizing material layer

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Hsinchu, Taiwan

Chien-Nan Lin