Realtek Semiconductor Inc.

National Applied Research Laboratories

National Chip Implementation Center National Applied Research Laboratories

National Chip Implementation Center

Epistar Corporation

Industrial Technology Research Institute

Chien-Ming Wu

Chun-Ming Huang

Shih-Hsiung Huang

Chen-Chia Chen

Chi-sheng Lin

Liang-Huan Lei

Chih-Lung Chen

Kai-Yin Liu

Chih-Chyau Yang

Jian-Ru Lin

Jie-Fan Lai

Shih-Lun Chen

Cheng-Pang Chan

Chin-Long Wey

Chi-Shi Chen

Tay-Her Tsaur

Wu-Tsung Lo

Chung-Ming Tseng

Gang-Neng Sung

Ta-Hsun Yeh

Chao-Cheng Lee

Shih-Chang Lee

Shih-Wei Wang

Shih-hsiung Huang

Chen-Chih Huang

Yi-Bing Lin

Chia-Lin Chang

Cheng-Cheng Yen

Chun-Yu Chen

Wei-Jyun Wang

Ming-Han Lee

Yung-Bin Lin

Ying-Cheng Wu

Su-Liang Liao

Yu-Chih Yang

Hui-Ming Lin

Pan Zhang

Kai-Yi Hong

Ming-Der Shieh

Shih-Hao Fang

Shing-Chung Tang

Chih-Chyan Yang

Chih-Hsing Lin

Wei-De Chien

The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

Successive approximation analog to digital conversion circuit and method having optimized linearity

The present invention provides an electroencephalogram measurement structure formed by an ear-hanging structure and a second circuit board. The ear-hanging structure includes a body. An ear-hanging member is disposed at the extension of the body. The body can be worn on the ear via the ear-hanging member. In addition, a first reference electrode and a second reference electrode are disposed on the body and coupled to a first circuit board. The first circuit board is coupled to an electrical jack; the second circuit board is coupled to the electrical jack via an electrical plug. Thereby, the electroencephalogram measurement can be performed simply by wearing the ear-hanging member on the ear of the person under test. Hence, the problems of complicated wiring and inconvenience in wearing can be solved concurrently.

Electroencephalogram measurement structure

An analog front-end circuit capable of dynamically adjusting gain includes a programmable gain amplifier (PGA) circuit, a sensor, a calculation circuit, a gain coarse control circuit and a gain fine control circuit. The PGA circuit includes an amplifier, a gain coarse adjustment circuit and a gain fine adjustment circuit. The gain coarse adjustment circuit is controlled by a coarse control signal, and a gain is adjusted in a coarse step according to an initial gain. The gain fine adjustment circuit is controlled by a fine control signal in a data mode, and the gain is adjusted in a fine step. The calculation circuit calculates a primary gain adjustment and a secondary gain adjustment. The gain coarse control circuit generates the coarse control signal according to the primary gain adjustment, and the gain fine control circuit generates the fine control signal according to the secondary gain adjustment.

Analog front-end circuit capable of dynamically adjusting gain

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

Pipeline analog to digital converter and timing adjustment method

A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

Flash analog to digital converter and calibration method

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

Flash analog to digital converter

A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.

Liquid level monitoring system and method

An echo cancellation circuit is coupled to a receiving circuit and a transmitting circuit of an electronic device, and the transmitting circuit includes an output transistor. The echo cancellation circuit includes first and second transistors, first and second resistor-capacitor networks (RC networks), and first and second resistors. The first transistor has a first gate, a first drain and a first source. The second transistor has a second gate, a second drain and a second source. The first drain and the second drain are coupled to the receiving circuit. The first RC network is coupled between the gate of the output transistor and the first gate. The second RC network is coupled between the first gate and the second gate. The first resistor is coupled between the first source and a reference voltage. The second resistor is coupled between the second source and the reference voltage.

Echo cancellation circuit

The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.

Communication apparatus and digital to analog conversion circuit thereof

Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.

Dual-path analog-front-end circuit and dual-path signal receiver

The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.

Electrostatic discharge protection circuit

A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.

Charge-pump boosting circuit

The present invention discloses an electrostatic discharge (ESD) protection circuit including: a first terminal configured to provide a first voltage having a first value in a normal mode; a second terminal configured to provide a second voltage having a second value in the normal mode; a detection circuit configured to provide a detection voltage according to the first and second voltages; and a protection circuit configured to operate in one of the normal mode and an ESD mode according to the detection voltage. When the difference between a value of the detection voltage and an average of the first and second values reaches a predetermined threshold, the protection circuit enters the ESD mode from the normal mode, and thereby has a first path between the first terminal and a grounding terminal and/or a second path between the second terminal and the grounding terminal be conductive for discharging abnormal energy.

The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.

Pipelined analog-to-digital converter

This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Electro-static discharge protection circuit

Growing community of inventors

Hsinchu, Taiwan

Chien-Ming Wu