United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Winbond Electronics Corporation

Chien-Ming Lu

Fu-Che Lee

Feng-Yi Chang

Chien-Cheng Tsai

Po-Han Wu

Chiu-Fang Hsu

A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.

Semiconductor memory structure and the method for forming the same

A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.

Method of forming semiconductor memory device having saddle portion

A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

Semiconductor memory device having a multilayer dielectric structure with a retracted sidewall below a bit line

A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

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Kaohsiung, Taiwan

Chien-Ming Lu