United Microelectronics Corp.

Chien-Ming Lai

Yi-Wen Chen

Chien-Ting Lin

Che-Hua Hsu

Hui-Ling Chen

Cheng-Hsien Chou

Chih-Hao Yu

Li-Wei Cheng

Tian-Fu Chiang

Ya-Huei Tsai

Guang-Hwa Ma

Yu-Ping Wang

Yen-Chen Chen

Sheng-Yao Huang

Jen-Po Huang

Tong-Jyun Huang

Chi-Mao Hsu

Ding-Lung Chen

Yao-Hung Liu

Hung-Yi Wu

Li Li Ding

Jung-Tsung Tseng

Qinggang Xing

Chun-Hsien Lin

Chien-Chung Huang

Yu-Ting Tseng

Ching-Hsiang Chiu

Zhi-Rui Sheng

Shih-Fang Tzou

Po-Chao Tsao

Chen-Ming Huang

Kun-Ju Li

Zhi-Cheng Lee

Chun-Tsen Lu

Lu-Sheng Chou

Yu-Tung Hsiao

Seng Wah Liau

Han Chuan Fang

En-Chiuan Liou

Ssu-I Fu

Chin-Fu Lin

Jiunn-Hsiung Liao

Kun-Hsien Lin

Chih-Wei Yang

Hsin-Fu Huang

Wen-Han Hung

Nien-Ting Ho

Rai-Min Huang

Ming-Tse Lin

Yu-Ru Yang

Chia-Fu Hsu

Cheng-Guo Chen

Po-Jui Liao

Jie-Ning Yang

Ying-Tsung Chen

Shao-Hua Hsu

Jian-Cun Ke

Guang-Yaw Hwang

Tsung-Yin Hsieh

Tzung-Ying Lee

Chun-Ting Yeh

Tsung-Lung Tsai

Hung-Ling Shih

Chung-Hsing Kuo

Mon-Sen Lin

Cheng-Yu Ma

Hao-Yeh Liu

Yu-Feng Liu

A semiconductor structure including a first substrate, a first conductive layer, and first bonding pads is provided. The first conductive layer is located on the first substrate. The first conductive layer includes a main body portion and an extension portion. The extension portion is connected to the main body portion and includes a terminal portion away from the main body portion. The first bonding pads are connected to the main body portion and the extension portion. The number of the first bonding pads connected to the terminal portion of the extension portion is plural.

Semiconductor structure

A semiconductor structure for wafer level bonding includes an interconnecting layer on a substrate, a bonding dielectric layer on the interconnecting layer, and a bonding pad in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface and physically contacting a dielectric portion of the interconnecting layer, and a sidewall between the top surface and the bottom surface. A bottom angle between the sidewall and the bottom surface is smaller than 90 degrees, and the bonding pad is not electrically connected to the interconnecting layer.

Semiconductor structure for wafer level bonding and bonded semiconductor structure

A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.

An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Oxide semiconductor field effect transistor

A semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface, and a sidewall between the top surface and the bottom surface. A bottom angle between the bottom surface and sidewall of the bonding pad is smaller than 90 degrees.

A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

Semiconductor structure formed with inductance elements

A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Method of forming oxide semiconductor field effect transistor

A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.

Structure of semiconductor device and method for bonding two substrates

Oxide semiconductor field effect transistor and forming method thereof

An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Manufacturing method of oxide semiconductor device

Oxide semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Semiconductor device with metal gate

A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Semiconductor device having metal gate with nitrogen rich portion and titanium rich portion

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Tainan, Taiwan

Chien-Ming Lai