Winbond Electronics Corporation

Windbond Electronics Corp.

Maxchip Electronics Corp.

Chien-Min Wu

Ping-Kun Wang

Shao-Ching Liao

Frederick Chen

He-Hsuan Chao

Ming-Che Lin

Chia-Hua Ho

Chih-Cheng Fu

Seow-Fong Lim

Chia Hua Ho

Min-Chih Wei

Kuang-Chih Hsieh

Chien-Chih Chen

Po-An Chen

Bo-Lun Wu

Seow Fong Lim

James Juen Hsu

Lu-Ping Chiang

Meng-Hung Lin

Shih-Hsien Yang

Yu-Ting Chen

Chi-Ching Liu

Norio Hattori

Meng-Heng Lin

Chih-Hua Hung

Chen-Lung Huang

Wen-Hsiung Chang

Chao-Hua Chang

Chi-Moon Huang

A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.

Semiconductor memory apparatus and testing method thereof

A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.

Write method for resistive memory

A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

Memory device

A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.

Resistive memory

A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.

Resistive memory apparatus and method for writing data thereof

A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.

Power on reset method for resistive memory storage device

A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

Memory storage apparatus and forming method of resistive memory device thereof

A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

Memory storage apparatus and forming method of resistive memory device

A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.

Circuit and method for memory operation

A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.

Resistive memory and control method thereof

A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.

One-time-programmable resistive random access memory and method for forming the same

A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

Resistive memory apparatus and setting method for resistive memory cell thereof

A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

Resistive random access memory with high-reliability and manufacturing and control methods thereof

A memory driving device and a method thereof applied for a RRAM array are provided. The memory driving device includes a voltage generator, a current detector, and a controller. The voltage generator generates a write voltage. An RRAM cell of the RRAM array is selected according to a selection signal for receiving the program voltage to generate a program current. The current detector detects the program current. The controller executes a driving procedure which includes: obtaining a voltage distribution for the program voltage; determining the initial voltage and the maximum voltage of the program voltage according to the voltage distribution; gradually increasing the program voltage from the initial voltage to the maximum voltage; determining whether the program current exceeds the reference current; and selecting another RRAM cell when the write current exceeds the reference current.

Devices and methods for selecting a forming voltage for a resistive random-access memory

The present invention provides an operation method for RRAM. The operation method includes providing a reset voltage pulse to a RRAM, providing a dummy voltage pulse to the RRAM, and providing a verification voltage pulse to the RRAM. The reset current of the RRAM is read when the verification voltage pulse is provided. The voltage level of the verification voltage pulse is higher than the voltage level of the read voltage pulse for reading the RRAM.

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Hsinchu, Taiwan

Chien-Min Wu