Powerchip Semiconductor Corporation

Powerchip Technology Corporation

Chien-Lung Chu

Chun-Hung Chen

Saysamone Pittikoun

Houng-Chi Wei

Wei-Chung Tseng

Ta-Chien Chiu

Jen-Chi Chuang

A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

Non-volatile memory and fabricating method thereof

A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

Method for fabricating non-volatile memory with ONO stack

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.

Semiconductor memory device with ONO stack

A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

Method of fabricating non-volatile memory

A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.

Method for manufacturing semiconductor device and non-volatile memory

A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.

Method of fabricating a non-volatile memory

A method of forming a stepped contact trench with doped trench sidewalls for shutting off parasitic edge transistors. The method includes the steps of forming a cap layer on a semiconductor substrate; sequentially forming a first dielectric layer and a second dielectric layer on the cap layer; etching a preliminary contact hole through the second dielectric layer and the first dielectric layer; implanting dopants in the substrate through the preliminary contact hole and then annealing to diffuse the dopants to form a first doped region; etching to remove the cap layer exposed by the preliminary contact hole; etching the substrate underneath the preliminary contact hole to form a trench with the doped region provided at the upper edges of the trench; isotropically etching the sidewalls of the preliminary contact hole with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a contact hole having a stepped sidewall; and etching to remove the cap layer exposed by the stepped contact hole.

Method of forming stepped contact trench for semiconductor devices

A method for forming a contact hole having a stepped sidewall is disclosed. First, a capping layer is formed on a semiconductor substrate, and then, a first dielectric layer and a second dielectric layer having different etch rates are formed on the capping layer. A preliminary contact hole is anisotropically etched through the layers, and part of the way through the substrate. After this, the sidewalls of the preliminary contact hole are isotropically etched with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a step sidewall. Finally, the exposed portions of the capping layer are removed to complete the contact hole fabrication.

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Hsinchu, Taiwan

Chien-Lung Chu