Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Ling Hwang

Ching-Hua Hsieh

Hsin-Hung Liao

Chung-Shi Liu

Pei-Hsuan Lee

Ying-Jui Huang

Bor-Ping Jang

Yu-Ting Chiu

Sung-Yueh Wu

Hao-Yi Tsai

Jui-Chang Kuo

Chen-Hua Douglas Yu

Tin-Hao Kuo

Chao-Wen Shih

Han-Ping Pu

Albert Wan

Jen-Chun Liao

Chuei-Tang Wang

Chung-Hao Tsai

Tzu-Chun Tang

Hsiao-Chung Liang

Kai-Chiang Wu

Chih-Hao Chang

Chun-Lin Lu

Yu-Chia Lai

Chih-Hsuan Tai

Yi-Li Hsiao

Tsung-Hsien Chiang

Chia-Hung Liu

Kuo-Lung Pan

Wei-Sen Chang

Chia-Sheng Huang

Jui-Pin Hung

Tzuan-Horng Liu

Ming-Che Ho

Yi-Wen Wu

Yeong-Jyh Lin

Jean Wang

Jeng-Nan Hung

Chung-Jung Wu

Wei-chih Chen

Tung Li Wu

Hsu-Chin Tseng

Disclosed are a bonding system and a bonding method. In one embodiment, the bonding system includes a chamber, first and second electrostatic chucks, a visible light sensor module and a nonvisible light module. The chamber is configured to provide a vacuum state. The first electrostatic chuck is configured to hold a first substrate having a first alignment mark in the chamber, wherein the first electrostatic chuck has a first window. The second electrostatic chuck is configured to hold a second substrate having a second alignment mark in the chamber, wherein the second electrostatic chuck has a second window. The visible light sensor module is configured to capture images of the first and the second alignment marks. The nonvisible light module is configured to capture a combined image of the first and second alignment marks via the first and second windows overlapping each other in the vacuum state.

Bonding system and method

A method for laminating a film to a wafer and apparatus for performing the lamination process are disclosed. The method includes providing the wafer and the film in a process chamber where the wafer and the film are separated from each other, achieving a vacuum state and a process temperature in the process chamber, and laminating the film to contact a surface of the wafer.

Lamination apparatus and method

A method and an apparatus for bonding semiconductor substrates are provided. The apparatus includes a first support configured to carry a first semiconductor substrate and a second semiconductor substrate bonded to each other, a gauging component embedded in the first support and comprising a fiducial pattern, and a first sensor disposed proximate to the gauging component, and configured to emit a light source towards the fiducial pattern of the gauging component.

Method and apparatus for bonding semiconductor substrate

A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.

Package system and manufacturing method thereof

A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.

Package structure and manufacturing method thereof

A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

Electronic device and manufacturing method thereof

A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

Semiconductor package and manufacturing method thereof

A semiconductor device includes an integrated circuit, first conductive features, second conductive features, a package structure, and an encapsulant. The integrated circuit has an active surface and a rear surface opposite to the active surface. The first conductive features surround the integrated circuit. The second conductive features are stacked on the first conductive features. The package structure is disposed on the second conductive features and the rear surface of the integrated circuit. The encapsulant laterally encapsulates the integrated circuit, the first conductive features, the second conductive features, and the package structure.

Semiconductor device and manufacturing method thereof

A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.

A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

Package structure

A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.

Method and system for thinning wafer thereof

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.

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Hsinchu, Taiwan

Chien-Ling Hwang