United Microelectronics Corp.

Other

Chien-Liang Wu

Sheng-Yuan Hsueh

Kuo-Hsing Lee

Te-Wei Yeh

Chih-Kai Kang

Kuo-Yu Liao

Guan-Kai Huang

Yi-Chung Sheng

Yi-Chun Chen

Yung-Chen Chiu

Chun-Hsien Lin

Po-Wen Su

Wen-Kai Lin

Chi-Horn Pai

A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

High electron mobility transistor and method for fabricating the same

An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

One-time programmable memory capacitor structure and manufacturing method thereof

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Magnetoresistive random access memory

A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

Resistor and resistor-transistor-logic circuit with GaN structure and method of manufacturing the same

A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

Semiconductor memory structure and fabrication method thereof

A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

One-time programmable (OTP) memory cell and fabrication method thereof

A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

High electron mobility transistor (HEMT) and forming method thereof

A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

Growing community of inventors

Tainan, Taiwan

Chien-Liang Wu