Cadence Design Systems, Inc.

Jasper Design Automation, Inc.

Chien-Liang Lin

Chung-Wah Norris Ip

Thiago Radicchi Roque

Andrea Iabrudi Tavares

Claudionor José Nunes Coelho

Thamara Karen Cunha Andrade

Claudionor José Nunes Coelho, Jr

Ronalu Augusta Nunes Barcelos

Igor Tiradentes Murta

Vitor Machado Guilherme Barros

Rafael Sales Medina Ferreira

Guilherme Henrique De Sousa Santos

Gabriel Peres Nobre

Marcos Augusto De Goes

Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

Analyzing waveform data generated for simulated circuit design

The present disclosure relates to a method for electronic design. Embodiments may include receiving, using a processor, an electronic design and performing formal verification upon at least a portion of the electronic design for a specific problem statement. Embodiments may further include generating a plurality of traces associated with the formal verification satisfying the specific problem statement and displaying, at a graphical user interface, an option to select at least one of the plurality of traces for display at the graphical user interface while the formal verification is performed.

System, method, and computer program product for displaying multiple traces while debugging during a formal verification

The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.

System, method, and computer program product for capture and reuse in a debug workspace

Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.

Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design

A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Manipulation of traces for debugging a circuit design

Manipulation of traces for debugging behaviors of a circuit design

A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.

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San Jose, CA, United States of America

Chien-Liang Lin