Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Mstar Semiconductor, Inc.

D-link Corporation

Neo Solar Power Corp.

Chien-Liang Chen

Harry Chuang

Wen-Chih Yang

Chun-Yu Lee

Chii-Horng Li

Chao-Min Lai

Shih-Ping Chou

Jin-Aun Ng

Yi-Suei Liao

Hao-Chieh Lee

Wen-Hung Lai

Bao-Ru Young

Chien-Hao Chen

Kuo-Tai Huang

Hao-Ming Lien

Jun-Lin Yeh

Kang-Cheng Lin

Maxi Chang

Chen-Lun Chiu

Ming-Tsung Tsai

Chung-Hau Fei

Chih Hao Hu

Chi Hsin Chang

Chun Ming Lin

Mong-Song Liang

Kuan-Yu Chen

Pei-Hsuan Lee

Po-Yuan Liu

Mong Song Liang

Hui-Chang Chen

Meng-Hsiu Wu

Chun-Ku Kuo

Cheng-Yu Lee

Ming-Yen Tsai

Kai-Yuan Siao

Hung-Wei Wang

Ssu-Yi Li

Chih-Chiang Chiu

Yu-Hsuan Huang

Chia-Chi Yeh

Ching-Huang Lin

Shih-An Yang

Chien-Jen Ke

Ssu-Yu Li

Hung-Yang Lin

Chang-Kuei Chung

Wen-Chin Yang

Chung-Hua Fei

Sen-Hsiang Hung

Chien-Hau Fei

Chii-Horng Lee

Wei-Hong Tsai

A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.

Multimedia device and operating method for system-on-chip

An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Electronic system and determination method capable of determining reason of cold boot event

In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N/N well structure, and/or a PMOS structure arranged next to a P/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.

In-line electrical detection of defects at wafer level

A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.

Power supply circuit

A performance management method and an electronic device are provided. The method is applied to the electronic device with a system processor and includes: sensing a temperature of the electronic device and determining whether the temperature is greater than a first temperature setting value; when the temperature is not greater than the first temperature setting value, initiating a frequency increasing procedure; when the temperature is greater than the first temperature setting value, determining whether the temperature is greater than a second temperature setting value, where the second temperature setting value is greater than the first temperature setting value; when the temperature is greater than the first temperature setting value and is not greater than the second temperature setting value, initiating a first frequency reducing procedure; and when the temperature is greater than the second temperature setting value, initiating a second frequency reducing procedure or turning off the system processor.

Power performance management method and electronic device

A media streaming device is provided that includes a media streaming module, a super capacitor and a protection module. The media streaming module provides the media stream. The super capacitor has a first terminal coupled to a power-supplying path and a second terminal coupled to a ground terminal. The protection module includes a current limiter and a disabling unit. The current limiter receives a power signal and performs current-limiting to generate a fixed-current power to charge the super capacitor and supply power to the media streaming module through the power-supplying path. The current limiter further detects a voltage of the first terminal of the super capacitor. The disabling unit disables the media streaming module when the voltage of the first terminal of the super capacitor is not higher than a voltage threshold value, and enables the media streaming module when the voltage is higher than the voltage threshold value.

Media streaming device and protection method of the same

A solar module frame includes two first borders and two second borders. At least one first border includes a first segment and a second segment, where one end of the first segment is connected to one end of the second border, and one end of the second segment is connected to one end of the other second border. The solar module frame includes at least one connection component. One end of the connection component is connected to the other end of the first segment, and the other end of the connection component is connected to the other end of the second segment. Each of the first segment, the second segment, and the connection component includes an external wall, a support wall, a first clamping wall, and a second clamping wall. Each of the first segment and the second segment includes an internal wall.

Solar module frame

A misalignment detection device comprising a first substrate, at least one integrated circuit, a second substrate, a third substrate, and at least one detection unit. The at least one integrated is disposed on the first substrate in a first pressing region. The third substrate is disposed on the first substrate in a second pressing region and on the second substrate on the second substrate in a third pressing region. The at least one detection unit outputs a fault signal in response to a positioning shift occurring in at least one of the first, second, and third pressing regions.

Misalignment detection devices

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor.

Power management method for a multi-microprocessor system

A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high.

Shift register with image retention release and method for image retention release

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Method of fabricating a sealing structure for high-k metal gate

A misalignment detection device comprising a substrate, at least one integrated circuit (IC), and at least one detection unit is disclosed. The substrate comprises a first positioning pad and a second positioning pad adjacent to the first positioning pad. The integrated circuit is disposed on the substrate and comprises a first positioning bump and a second positioning bump adjacent to the first positioning bump. The first and second positioning bumps substantially correspond to the first and second positioning pads, respectively. The at least one detection unit is electrically coupled to the substrate, wherein the detection unit outputs a fault signal in response to a positioning shift occurring between the first and second positioning pads and the first and second positioning bumps.

A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit.

Touch panel display

A flexible printed circuit and a display module comprising the flexible printed circuit are disclosed. The display module comprises a display panel, a printed circuit board, and a flexible printed circuit. The flexible printed circuit electrically connects the display panel and the printed circuit board, and further comprises a flexible substrate and a cover lay. The flexible substrate has an upper surface and two opposite end portions. The cover lay is disposed on the upper surface of the flexible substrate and extends along a lengthwise direction of the flexible substrate. The cover lay further has two opposite sides each also extending along the lengthwise direction of the flexible substrate. Each of the sides has at least a partially continuous contour which is formed with a discontinuous status on at least one of the end portions.

Flexible printed circuit and display module comprising the same

Growing community of inventors

Hsinchu, Taiwan

Chien-Liang Chen