Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Chien-Kuo Yang

Ta-Chuan Liao

Yi-Shao Liu

Chun-Wen Cheng

Wei-Cheng Lin

Jui-Cheng Huang

Felix Ying-Kit Tsui

Tung-Tsun Chen

Fei-Lung Lai

Chun-Yao Ko

Hua-Chou Tseng

Cheng-Wen Fan

Jing-Hwang Yang

Chan-Ching Lin

Yu-Ho Chiang

Chih-Yuh Tzeng

Victor Chiang Liang

Cheng-Hsiang Hsieh

Der-Yuan Wu

Shih-Hsien Chen

Steve S Chung

Liang-Tai Kuo

Victor-Chiang Liang

Mark Chen

Shang-Jr Chen

Ching-Chun Hwang

Wei-Chung Chen

A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

Biological device and biosensing method thereof

Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.

Biosensor devices and methods of forming the same

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.

Backside sensing BioFET with enhanced performance

Backside sensing bioFET with enhanced performance

The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

Structure and method for single gate non-volatile memory device having a capacitor well doping design with improved coupling efficiency

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Method for reducing capacitance variation between capacitors

Structure of capacitor set

A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 &angst;-16 &angst; gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

Direct determination of interface traps in MOS devices

A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type grade therein, and then the second photoresist layer of low-voltage MOS region is removed. Moreover, spacers are formed on sidewall of said gates of high-voltage MOS and low-voltage MOS, and then a second dielectric layer is formed on the substrate of high-voltage and low-voltage MOS.

Method for producing a high-voltage and low-voltage MOS transistor with salicide structure

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Taipei, Taiwan

Chien-Kuo Yang