United Microelectronics Corp.

Ili Technology Corporation

Myson Century, Inc.

Chien-Kuo Wang

Chen-Hsien Hsu

Wen-Jung Liao

Yung-Chang Lin

Chun-Liang Hou

Wei-Jen Wang

Ruey-Chyr Lee

Kao-Su Huang

Ta-Chuan Yeh

Chen-Jung Chuang

Yu-Ming Sun

Dar-Sun Tsien

Ni-Min Chung

Tsuoe-Hsiang Liao

Tsen-Shau Yang

Yuan-Che Lee

Te-Chang Wu

Chen-Ting Kuan

Ming-Yu Tsai

Kuey-Lung Hsueh

Ta-Cheng Lin

Tai-Chi Kao

Chin-Chieh Chao

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

Semiconductor structure and testing method using the same

A test key structure includes a plurality of transistors formed on a scribe line of a wafer and arranged in a 2*N array having 2 columns and N rows. The transistors arranged in the 2*N array respectively includes a gate, a source, a drain, and a body. All of the sources of the transistors arranged in the 2*N array are electrically connected to each other.

Test key structure and test key group

A method for image data compression of a to-be-encoded image block includes: determining one of a plurality of preset encoding modes as an encoding mode based upon attributes of pixels of the to-be-encoded image block; and compressing image data of the to-be-encoded image block according to the encoding mode thus determined so as to obtain encoded data.

Method for image data compression of image block

A multiplexer includes: a first switch unit coupled between a first input terminal and an output terminal and including a series connection of first and second switches; a second switch unit coupled between a second input terminal and the output terminal; and a third switch unit coupled to a third input terminal and a common node between the first and second switches. Different first and second voltages, and a third voltage greater than one of the first and second voltages and less than the other one of the first and second voltage are applied respectively to the first, second and third input terminals. The multiplexer is operable between a first mode, where the first voltage is transmitted to the output terminal, and a second mode, where the second voltage is transmitted to the output terminal and the third voltage is transmitted to the common node between the first and second switches.

Multiplexer and multiplexing method for use with the same

An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped region of the first conductivity type. The well region is configured in the substrate. The first doped region is configured in the well region. The second doped region is configured in the well region and surrounding the first doped region. The third doped region is configured in the well region and surrounding the first doped region and the second doped region. The fourth doped region is configured in the well region and under the first doped region and the second doped region. The fourth doped region is coupled with the first doped region and with the second doped region, respectively.

ESD protection device having reduced equivalent capacitance

A voltage multiplying circuit comprising: a first capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the first capacitor is selectively coupled to a first voltage or a second voltage, and the second terminal is selectively coupled to the first voltage or a fourth voltage; a second capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the second capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the second capacitor is selectively coupled to a third voltage or the fourth voltage; and a third capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the third capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the third capacitor is selectively coupled to a third voltage or the fourth voltage.

Voltage multiplying circuit utilizing no voltage stabling capacitors

A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.

Method of manufacturing a capacitor deep trench and of etching a deep trench opening

A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp.

Electrostatic discharge immunizing circuit without area penalty

A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS transistor is connected to a second voltage source and the source/drain of the first PMOS transistor is connected to a first voltage source. The tie low circuit includes a second NMOS transistor and a second PMOS transistor and the tie high circuit includes a third NMOS transistor and a third PMOS transistor.

Filler circuit cell

A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Defect detection system with multilevel output capability and method thereof

IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating critical dimensions of a standard cell in a plurality of surroundings, generating a plurality of circuit parameters corresponding to the plurality of surroundings, calculating the differences of the plurality of circuit parameters and the ideal circuit parameter of the standard cell, and analyzing the distribution of the differences.

Method for determining a standard cell for IC design

A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the analysis result, and piecing together the leaf cell layouts to generate the standard cell layout.

Method of generating a standard cell layout and transferring the standard cell layout to a substrate

A single-ended high-voltage level shifter for a TFT-LCD gate driver comprises a high-voltage power supply and a low-voltage power supply, a low-voltage NMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor. An input signal is applied at the gate of the low-voltage NMOS transistor. The source of the low-voltage NMOS transistor is connected to the low-voltage power supply. The source of the high-voltage NMOS transistor is connected to the drain of the low-voltage NMOS transistor. The high-voltage NMOS transistor has a first reference voltage applied at its gate. The level of the first reference voltage is between the input-signal level and the high-voltage power supply. The drain of the high-voltage PMOS transistor is connected to the drain of the high-voltage NMOS transistor. The source of the high-voltage PMOS transistor is connected to the high-voltage power supply. The high-voltage PMOS transistor has a second reference voltage applied at its gate. The second reference voltage keeps the high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage. The drain of the high-voltage PMOS transistor is employed as the output end connected to an output buffer of the next stage.

Growing community of inventors

Hsinchu, Taiwan

Chien-Kuo Wang