Industrial Technology Research Institute

Silicon Touch Technology Inc.

Chien-kuo Tien

Kun-Cheng Wu

Ruey-Liang Ma

Ching-Tang Chang

Chia-Chang Hsu

Dze-chaung Wang

A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.

System for packing variable length instructions into fixed length blocks

A motor drive circuit includes an amplifying and comparing circuit, a multiplexer, an input control circuit and a drive pulse generator. The amplifying and comparing circuit receives an output signal from a Hall element and generates an amplified output signal. The input control circuit detects whether the Hall element is a Hall sensor or a Hall IC for controlling the multiplexer to have its output from either the Hall IC or the amplifying and comparing circuit. The drive pulse generator has an input connected to the output of the multiplexer, and has four outputs connected to four MOS transistors respectively for generating clock signals to drive the four MOS transistors to provide driving current to the motor.

DC brushless motor drive circuit having input signal compatability to

An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed. The method comprises the steps of: (a) obtaining an instruction buffer comprising a plurality of entries, each entry comprising a random access memory (RAM) portion and a content addressable memory (CAM) portion for storing result data and source operand tag, respectively, wherein the CAM portion also contains means for linking with an associated RAM portion and the result data contains an instruction; (b) providing a result bus capable of transmitting the result data and a result tag; (c) matching the result tag in the result bus with the source operand tag in the CAM, and writing the result data into the RAM portion of an entry if the result tag in the result bus matches the source operand tag of an associated CAM portion; and (d) issuing ready instructions and changing the source operand tag in a corresponding CAM in such a manner that the entry containing the CAM will be identified as an empty entry so as to all new instruction to be written thereto. Because instructions are stored in the RAM in an out-of-order, a linear systolic array is provided so as to keep the sequence of instructions in order. The linear systolic array, which can be easily compressed, allows the prioritization of instructions for issue among ready instructions, and the handling branch mis-prediction and faults to be implemented.

Growing community of inventors

Taipei, Taiwan

Chien-kuo Tien