Lattice Semiconductor Corporation

Chien Kuang Chen

Fulong Zhang

John Schadt

Zheng Chen

A margin circuit for controlling skew between first and second signals in order to determine margin, includes a variable delay circuit and a margin controller. Based on a current code value, the delay circuit applies a delay to the second signal to generate a delayed second signal. The margin controller generates the current code value for the variable delay circuit to be any one of a plurality of available code values. In one embodiment, the margin circuit is a write margin circuit that generates a first clock signal and a delayed second clock signal used to generate transmit (TX) clock and data signals having a non-zero phase offset between them. In another embodiment, the margin circuit is a read margin circuit that applies a phase offset between receive (RX) clock and data signals to enable the RX clock signal to be used to recover data from the RX data signal.

In-system margin measurement circuit

In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8&#xd7;1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4&#xd7;1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4&#xd7;1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

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San Jose, CA, United States of America

Chien Kuang Chen