Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Semiconductor Manufacturing Corp.

Chien-Jung Wang

Jian-Hong Lin

Chewn-Pu Jou

Pei-Haw Tsao

Huan-Neng Chen

Ling-Sung Wang

Chin-Shan Wang

Chingfu Lin

Hsueh-Chung Chen

Lien-Jung Hung

Yi-Lung Cheng

Bi-Ling Lin

Yih-Yuh Doong

Chwei-Ching Chiu

Su-Chen Fan

Chien Shih Tsai

Shih-Liang Wang

Shou-Chung Lee

Sung Chun Hsieh

Chin Chuan Peng

Ming-Zong Lin

Ding-Da Hu

Chao-Hao Cheng

Tsu-bin Shen

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Semiconductor structure and manufacturing method thereof

A method of forming an integrated circuit comprises forming a first doped region and a second doped region in a substrate. The second doped region is formed separate from the first doped region by a first spacing. A dielectric layer is formed over the substrate, and a gate is formed over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate, opposite the first substrate side of the gate. A third doped region is formed in the substrate separated from the first doped region by a second spacing. The method further comprises forming a fourth doped region in the substrate.

Method of forming bandgap reference integrated circuit

A method includes charging a capacitor connected to an input node, gradually decreasing an output voltage at an output node, and electrically connecting the input node to the output node. A circuit that performs the method is also disclosed. A system that includes the circuit is also disclosed.

Circuit with a droop compensating mechanism

An integrated circuit comprises a first doped region and a second doped region in a substrate. The second doped region is separated from the first doped region by a first spacing. The integrated circuit further comprises a dielectric layer over the substrate and a gate over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate opposite the first substrate side of the gate. The integrated circuit also comprises a third doped region in the substrate separated from the first doped region by a second spacing. The integrated circuit further comprises a fourth doped region in the substrate. The gate and the third doped region are coupled with a first voltage supply, and the fourth doped region is coupled with a second voltage supply.

Bandgap reference circuit

One or more systems and techniques for managing one or more electronic devices are provided. A determination is made that a first capacitor in a set of one or more capacitors has a defect. Responsive to the determination, the first capacitor is disabled, and a second capacitor is enabled.

MiM capacitor

A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.

Metal oxide metal capacitor with slot vias

A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Method of forming an interconnect structure having an enlarged region

A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Seal ring structures with reduced moisture-induced reliability degradation

A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.

An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Growing community of inventors

Hsinchu, Taiwan

Chien-Jung Wang